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    <title>i.MX ProcessorsのトピックRe: Is there any solution for SATA BIST?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306559#M39492</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The BIST operation on the i.MX6D/Q is described on section 53.3.5.13 of the i.MX6D/Q Reference Manual (link below). The supported modes are BIST-L (Loopback) both as responder or initiator and are controlled by the register SATA_BISTCR. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 11 Apr 2014 21:03:48 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2014-04-11T21:03:48Z</dc:date>
    <item>
      <title>Is there any solution for SATA BIST?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306558#M39491</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to verify SATA-I/F on the i.MX6 original board.&lt;/P&gt;&lt;P&gt;Is it possible in i.MX6 to work the static test mode for BIST-L or BIST-TSA?&lt;/P&gt;&lt;P&gt;Is there any solution for it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;George&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 31 Mar 2014 02:05:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306558#M39491</guid>
      <dc:creator>george</dc:creator>
      <dc:date>2014-03-31T02:05:32Z</dc:date>
    </item>
    <item>
      <title>Re: Is there any solution for SATA BIST?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306559#M39492</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The BIST operation on the i.MX6D/Q is described on section 53.3.5.13 of the i.MX6D/Q Reference Manual (link below). The supported modes are BIST-L (Loopback) both as responder or initiator and are controlled by the register SATA_BISTCR. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 11 Apr 2014 21:03:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306559#M39492</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2014-04-11T21:03:48Z</dc:date>
    </item>
    <item>
      <title>Re: Is there any solution for SATA BIST?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306560#M39493</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear gusarambula,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks you for your response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;George&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 14 Apr 2014 06:15:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306560#M39493</guid>
      <dc:creator>george</dc:creator>
      <dc:date>2014-04-14T06:15:39Z</dc:date>
    </item>
    <item>
      <title>Re: Is there any solution for SATA BIST?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306561#M39494</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dears,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; We check kernel 3.10.17-r0 Ahci.h (Line:82~89), some sample code as below:&lt;/P&gt;&lt;P&gt;/* global controller registers */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_CAP = 0x00, /* host capabilities */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_CTL = 0x04, /* global host control */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_IRQ_STAT = 0x08, /* interrupt status */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_VERSION = 0x10, /* AHCI spec. version compliancy */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_EM_LOC = 0x1c, /* Enclosure Management location */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_EM_CTL = 0x20, /* Enclosure Management Control */&lt;/P&gt;&lt;P&gt;&amp;nbsp; HOST_CAP2 = 0x24, /* host capabilities, extended */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We no see any destination about BIST.&lt;/P&gt;&lt;P&gt;Can any one give me some sample code to help to implement?&lt;/P&gt;&lt;P&gt;How can I enable the BIST test?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Yao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jun 2015 11:18:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-there-any-solution-for-SATA-BIST/m-p/306561#M39494</guid>
      <dc:creator>yaolinchang</dc:creator>
      <dc:date>2015-06-04T11:18:51Z</dc:date>
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