PF0100 question

jwu — Fri, 28 Mar 2014 01:51:32 GMT

In section 6.1.2.1 of the datasheet, it seems that the startup sequence is determined by timeslot only, not the power good status of individual regulators. If I wanted a sequence such as SW1 - SW3 - SW4 - SW2, a register must exist to specify that SW3's
turn-on event is the power-good status of SW1, but this register does not seem to exist.

Can you confirm that this is the case? If it is, the startup sequence will continue regardless of whether each individual regulator has reached its power good status or not. In the above example, if SW3*IN is still at 0V when SW4 has already started, the power-on sequence will not work.

Re: PF0100 question

igorpadykov — Mon, 31 Mar 2014 10:04:57 GMT

Hi, John

yes, startup sequence is not determined by power good status of individual regulators.

However there is fault mode (described on p.17 MMPF0100 Datasheet).

If fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW.

After 100 ms typically part will power off. To enter the fault mode, set bit

OTP_PG_EN of register OTP PWRGD EN to 1.

Also p.35 tells that each buck regulator has a programmable current limit.

In an overcurrent condition, if the current limit condition persists for more than

8.0 ms, a fault condition is generated.

LDOs have REGSCPEN bit, if REGSCPEN=1 LDO will be disabled.

Default REGSCPEN=0 (current limit), check p.84

MMPF0100 Datasheet (rev.6, 8/2013)

http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf

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