topic Re: Single Synchronous EIM Access in i.MX Processors

Single Synchronous EIM Access

tom1 — Tue, 25 Mar 2014 17:48:36 GMT

Hi,

Figures 12 and 13 of the i.MX6 Dual/Quad Applications Products for Industrial Products data sheet show single read and write synchronous accesses on the EIM bus. Can someone explain how those are achieved?

I assume an AXI read or write with burst length of 1 and burst size of 2(for a 16 bit data bus) would cause a single read or write synchronous access? I am accessing registers in an FPGA and do not want to burst any data to/from the registers - only read or write single data words.

Would accessing a non-cached uint16 cause the proper AXI access?

And, is BL ignored if a single AXI access is used?

Thanks for your time,

Tom

Re: Single Synchronous EIM Access

Yuri — Fri, 28 Mar 2014 07:52:10 GMT

Note, the Figures 12 and 13 of the Datasheet should be considered mainly as

demonstration material,where waveforms are used to show (emphasize) some

timing parameters. You are right, the waveforms correspond to burst length of 1,

but note, the i.MX6 EIM does not allow it : minimal value for burst length BL is

4 beats.

Have a great day,
Yuri

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Re: Single Synchronous EIM Access

tom1 — Wed, 02 Apr 2014 12:52:41 GMT

OK. I will switch to asynchronous mode since single word transfers are impossible in synchronous mode.

Thanks,

Tom

Re: Single Synchronous EIM Access

abhijeet_ghodga — Tue, 03 Mar 2020 04:11:46 GMT

Hi Tom,

Did the synchronous mode prove useful for audio data transfer over EIM?

Best,

Abhijeet