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    <title>topic Re: PCIE link up problem in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302867#M38457</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for you reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.For the bsp,I get it from freescale chinese FAE last year,and the BSP name is kernel-3.05.tar.bz2,I can not&amp;nbsp; get more information about release date.Bypass it, I will download &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;L3.0.35_4.1.0_130816_source.tar.gz&lt;/SPAN&gt; and try this afternoon.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.For the clock enabe,I see it has been enabled in function _clk_cpie_enable.And I have&amp;nbsp; refer to this &lt;A _jive_internal="true" href="https://community.nxp.com/message/380425#380425"&gt;https://community.freescale.com/message/380425#380425&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Mar 2014 04:30:32 GMT</pubDate>
    <dc:creator>thouswave</dc:creator>
    <dc:date>2014-03-25T04:30:32Z</dc:date>
    <item>
      <title>PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302865#M38455</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Hello.&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;I am debugging the PCIE unit of our own IMX6Q board,till now,PCIE can not link up.&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;1.The attach file is our schematic,is there any problem with schematic.For addition,signal PCIE_RST_N and PCIE_PRSNT1 has been checked,and no problem is found.CLK signal is 100M.&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;2.Our PCIE EP device is (10/100/1000Mbps)NIC，and the Instructions says it supports PCI Express 1.0a。The IMX6Q PCIE PHY support&amp;nbsp; Revision 2.0 and&amp;nbsp; Revision 1.1.So if there is some compliance problem?&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;3.Since we just use the NIC device to check our PCIE unit,so we can choice some other device as well.What is the EP device that freescale use it to check their own board,if I can use it,our develop can be easier.&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Any one can help me? Any idea is welcome.&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Mar 2014 02:14:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302865#M38455</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-25T02:14:38Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302866#M38456</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Which BSP are you using? I recommend you using the newest L3.0.35_4.1.0_130816_source.tar.gz BSP. And the PCIe clock output should be enabled in the code when the IMX6 worked as RC. Have you enabled the pcie clock yet?&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Dan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Mar 2014 03:25:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302866#M38456</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2014-03-25T03:25:44Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302867#M38457</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for you reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.For the bsp,I get it from freescale chinese FAE last year,and the BSP name is kernel-3.05.tar.bz2,I can not&amp;nbsp; get more information about release date.Bypass it, I will download &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;L3.0.35_4.1.0_130816_source.tar.gz&lt;/SPAN&gt; and try this afternoon.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.For the clock enabe,I see it has been enabled in function _clk_cpie_enable.And I have&amp;nbsp; refer to this &lt;A _jive_internal="true" href="https://community.nxp.com/message/380425#380425"&gt;https://community.freescale.com/message/380425#380425&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Mar 2014 04:30:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302867#M38457</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-25T04:30:32Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302868#M38458</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;You can try to use the newest &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;L3.0.35_4.1.0_130816_source.tar.gz first. And for the clock enabe, refer to that thread is correct. If any problem contact us~~&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Best Regards&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Dan&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Mar 2014 05:45:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302868#M38458</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2014-03-25T05:45:07Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302869#M38459</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have try the new BSP,I config it as PCIE RC mode,unfortunately,PCIE still link down.Following is kernel log:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.628152] cpaddr = ea880000 suspend_iram_base=ea8f0000&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.633576] PM driver module loaded&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.637175] iMX6 PCIe PCIe RC mode imx_pcie_pltfm_probe entering.&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.744760] PCIE: imx_pcie_pltfm_probe start link up.&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.355105] link up failed, DB_R0:0x00000602, DB_R1:0x08000000!&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.361046] IMX PCIe port: link down!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;PS:DR_R0 value is not same every time.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Mar 2014 02:00:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302869#M38459</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-26T02:00:51Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302870#M38460</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/richard.zhu"&gt;richard.zhu&lt;/A&gt;, would you please help this issue about "pcie link up problem"?&lt;/P&gt;&lt;P&gt;Thanks a lot~~&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Dan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Mar 2014 06:21:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302870#M38460</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2014-03-26T06:21:05Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302871#M38461</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have modify code to print DB_R0 register during tring to link,and I find that xmlh_ltssm_state filed only have one time change:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.982642] 0x00359E00,0x08200000,0x00000004&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.989996] 0x0047D900,0x08200000,0x00000004&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.997338] 0x00000602,0x08000000,0x00000002&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.004398] 0x004A4A02,0x08000000,0x00000002&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.011723] 0x004A4A02,0x08000000,0x00000002&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.019069] 0x002CF742,0x08000000,0x00000002&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you tell me what doed the STATE 2 mean?In datasheet,it says [xmlh_ltssm_state LTSSM current state. See source for encodings],I am sorry I still do not know where is [source for encodings].&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Mar 2014 07:25:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302871#M38461</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-26T07:25:53Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302872#M38462</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Why &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;rc&lt;/SPAN&gt; mode is configured?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;As I remember that the explicit PCIE RC/EP modes are used in FSL PCIE RC/EP validation system only.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Richard.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Mar 2014 08:51:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302872#M38462</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-26T08:51:11Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302873#M38463</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for your Attention.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am sorry that I have not understand your words exactly.I said I config it as RC mode,detail is as following in menuconfig:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;System Type&amp;nbsp;&amp;nbsp; ---&amp;gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Freescale MXC Implementations&amp;nbsp;&amp;nbsp; ---&amp;gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; [ * ] PCI Express support&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; [&amp;nbsp;&amp;nbsp; ]&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PCI Express EP mode in the IMX6 RC/EP interconnection system&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; [ * ]&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PCI Express RC mode in the IMX6 RC/EP interconnection system&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Am I wrong?If my config is wrong,can you tell me the right config.Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Mar 2014 09:51:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302873#M38463</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-26T09:51:30Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302874#M38464</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;DO NOT select PCI Express RC mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Because they are only used in iMX6 &lt;SPAN class="SpellE"&gt;PCIe&lt;/SPAN&gt; EP/RC validation system.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="margin:0in;margin-bottom:.0001pt;line-height:18.0pt"&gt;&lt;SPAN style="font-size:10.0pt;font-family: inherit , serif ;mso-bidi-font-family:Arial"&gt;[ ] PCI Express EP mode in the IMX6 RC/EP interconnection system &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin:0in;margin-bottom:.0001pt;line-height:18.0pt;outline: 0;font-weight:inherit;font-style:inherit"&gt;&lt;SPAN style="font-size:10.0pt;font-family: inherit , serif ;mso-bidi-font-family:Arial"&gt;[ * ] PCI Express RC mode in the IMX6 RC/EP interconnection system &lt;/SPAN&gt;&lt;/P&gt;&lt;P style="outline: 0;font-weight:inherit;font-style:inherit;min-height: 8pt"&gt;&lt;/P&gt;&lt;P style="margin:0in;margin-bottom:.0001pt;line-height:18.0pt"&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:12.0pt"&gt;Enable this one "&lt;/SPAN&gt;&lt;SPAN style="font-size:10.0pt;font-family: inherit , serif ;mso-bidi-font-family:Arial"&gt;[ * ] PCI Express support &lt;/SPAN&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:12.0pt"&gt;” is enough at your side.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin:0in;margin-bottom:.0001pt;line-height:18.0pt"&gt;&lt;/P&gt;&lt;P style="margin:0in;margin-bottom:.0001pt;line-height:18.0pt"&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:12.0pt"&gt;Richard.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Mar 2014 02:00:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302874#M38464</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-27T02:00:25Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302875#M38465</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Understand now,I have tried that,but no effect.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got a new phenomenon.I have two PCIE EP device on hand,different device is inserted,different phenomenon happened.In function {&amp;nbsp; imx_pcie_link_up&amp;nbsp; },I add the following source:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ltssm = readl(dbi_base+DB_R0) &amp;amp; 0x3F;&lt;/P&gt;&lt;P&gt;+ printk("0x%.8X,0x%.8X,0x%.8X\n",readl(dbi_base+DB_R0),readl(dbi_base+DB_R1),rx_valid);&lt;/P&gt;&lt;P&gt;if((ltssm == 0xD) &amp;amp;&amp;amp; ((rx_valid &amp;amp; 0x1)==0)) {&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;One EP device's phenomenon is:&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.982642] 0x00359E00,0x08200000,0x00000004&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.989996] 0x0047D900,0x08200000,0x00000004&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.997338] 0x00000602,0x08000000,0x00000002&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.004398] 0x004A4A02,0x08000000,0x00000002&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.011723] 0x004A4A02,0x08000000,0x00000002&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 2.019069] 0x002CF742,0x08000000,0x00000002&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; color: #3d3d3d;"&gt;While the other EP device's phenomenon is:&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.883904] 0x00590E00,0x08200000,0x00000004&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.891322] 0x0050CF00,0x08200000,0x00000004&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.898738] 0x002CF742,0x08000000,0x00000006&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.905710] 0x004A4A02,0x08000000,0x00000006&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.913021] 0x004A4A02,0x08000000,0x00000006&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.920340] 0x004ABC43,0x08000000,0x00000006&lt;/P&gt;&lt;P&gt;[&amp;nbsp;&amp;nbsp;&amp;nbsp; 1.927648] 0x00B5BC43,0x08000000,0x00000006&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Link training state can be different,so I doubt if some problem with hardware.As I known,PCIE link training state will change as following:&lt;/P&gt;&lt;P&gt;Detect --&amp;gt; Polling --&amp;gt; Configuration --&amp;gt; LO&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But now I do not know what is the state now of my board link training.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Mar 2014 04:32:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302875#M38465</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-27T04:32:16Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302876#M38466</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This problem is solved.We have change the EP device.&lt;/P&gt;&lt;P&gt;Now we use a FPGA board with SPARTAN-6 that produces by our company,and link up successfully.&lt;/P&gt;&lt;P&gt;It just so happens that our next project is a board IM6Q+SPARTAN-6.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Mar 2014 06:02:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302876#M38466</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-28T06:02:31Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302877#M38467</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi，&lt;/P&gt;&lt;P&gt;It's great news you have solved your problem. :smileyhappy:&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Dan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Mar 2014 06:17:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302877#M38467</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2014-03-28T06:17:53Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302878#M38468</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Hongxing,&lt;/P&gt;&lt;P&gt;Thanks a lot for your help. The customer have solved this problem.&lt;/P&gt;&lt;P&gt;Have a nice day~~&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Dan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Mar 2014 06:19:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302878#M38468</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2014-03-28T06:19:30Z</dc:date>
    </item>
    <item>
      <title>Re: PCIE link up problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302879#M38469</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now,our device has been identified,but our device driver can not be install because of the IRQ.&lt;/P&gt;&lt;P&gt;I cat the file /proc/interrupts and find that no pcie IRQ is registed.From IMX6DQRM.pdf,I find IRQ 152-155 is PCIE IRQ.&lt;/P&gt;&lt;P&gt;So,do you have any patch to enable PCIE IRQ,either MSI or INTX is OK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 28 Mar 2014 09:19:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIE-link-up-problem/m-p/302879#M38469</guid>
      <dc:creator>thouswave</dc:creator>
      <dc:date>2014-03-28T09:19:42Z</dc:date>
    </item>
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