i.MX6 IPU DIsplay interface sync pulses

andreas81 — Thu, 20 Mar 2014 07:55:29 GMT

Hi,

we are working at the moment with i.MX6DL. I tried to setup new display support (RGB interface) in Bootloader U-Boot. There is a struct available, where I can define all the display timings:

	.mode	= {
		.name = "wvga-rgb",
		.refresh = 57,
		.xres = 800,
		.yres = 480,
		.pixclock = 33260,
		.left_margin = 42,
		.right_margin = 86,
		.upper_margin = 10,
		.lower_margin = 33,
		.hsync_len = 128,
		.vsync_len = 2,
		.sync = 0,
		.vmode = FB_VMODE_NONINTERLACED

But there I miss the activity of the sysnc pulses, e.g. if hsync is active high or active low. I also searched in the user manual about the i.MX6 IPU register where I can set the active high or low information but I can't find it.

So can anybody tell me in which registers I can set the following informations:

V-Sync: Active high or low

H-Sync: Active high or low

Pixel Clock: Data is driven on falling or rising edge

Output enable: Active high or low

Data lines: inverted or not

If anybody can tell me how I can do this in U-Boot it would also help.

Best regards,

Andreas

Re: i.MX6 IPU DIsplay interface sync pulses

qiang_li-mpu_se — Fri, 30 May 2014 09:02:15 GMT

The HSYNC, VSYNC, Pixel clock polarity was set the register IPU_DI_GENERAL; the DE and data line polarity was set in register IPU_DI_POL.

In followed link, there is sample code to enable the LCD interface display in Uboot: https://community.freescale.com/docs/DOC-98109

i.MX Processorsのトピックi.MX6 IPU DIsplay interface sync pulses

i.MX6 IPU DIsplay interface sync pulses

Re: i.MX6 IPU DIsplay interface sync pulses