Reading data from an FPGA connected to the iMX6q EIM bus

nishad_kamdar — Fri, 18 Apr 2014 08:00:24 GMT

Hi,

I have been trying to do this for quite some time now,

I have a custom imx6Q board which has the 25 Address lines, Lower order 16 bit data bus , OE, WE and CS1 connected to an Altera FPGA.

My aim was to generate a ROM in the FPGA and read it from the Microprocessor.

I was successfully able to do it. I will explain the steps below in order to replicate the scenario.

Step 1: Build the Ltib with Sabre-AI_weimnor u-boot and Sabre-AI kernel.

Assert the following in the kernel configuration

CONFIG_MTD_ROM=y

and make sure,

CONFIG_MTD_PHYSMAP=y

Step 2: I have attached the board-mx6q_sabreauto.c and board-mx6q_sabreauto.h files so that you may find the register settings and the iomux settings there.

In board-mx6q_sabreauto.h:

static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = {

/* Parallel NOR */

MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,

MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,

MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1,

/*Control NOR reset using gpio mode*/

/* Parallel Nor Data Bus */

MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0,

MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1,

MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2,

MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3,

MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4,

MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5,

MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6,

MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7,

MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8,

MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9,

MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10,

MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11,

MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12,

MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13,

MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14,

MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15,

/* Parallel Nor 25 bit Address Bus */

MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25,

MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24,

MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,

MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,

MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,

MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,

MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,

MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,

MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,

MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,

MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,

MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,

MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,

MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,

MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,

MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,

MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,

MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,

MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,

MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,

MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,

MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,

MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,

MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,

MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,

};

In board-mx6q_sabreauto.c :

static void mx6q_setup_weimcs(void)

{

void __iomem *nor_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);

void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);

////////////////////*******************************///////////////////////

void __iomem *mx6q_iomuxc_reg = MX6_IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR);

////////////////////*******************************///////////////////////

unsigned int reg;

struct clk *clk;

u32 rate;

/* CLKCTL_CCGR6: Set emi_slow_clock to be on in all modes */

reg = readl(ccm_reg + 0x80);

reg |= 0x00000C00;

writel(reg, ccm_reg + 0x80);

clk = clk_get(NULL, "emi_slow_clk");

if (IS_ERR(clk))

printk(KERN_ERR "emi_slow_clk not found\n");

rate = clk_get_rate(clk);

if (rate != 132000000)

printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"

" WEIM NOR timing may be incorrect!\n");

/* For EIM chip select configuration

* map the 128MB to chip select 2 which

* is connected to the FPGA.

* IOMUXC_GPR1:

* ADDRS3[10] = 00;

* ACT_CS3 = 0;

* ADDRS2[10] = 00;

* ACT_CS2 = 0;

* ADDRS1[10] = 10;

* ACT_CS1 = 1;

* ADDRS1[10] = 00;

* ACT_CS1 = 0;

writel(0x48400028, mx6q_iomuxc_reg + 0x00000004);

writel(0x00610081, nor_reg + 0x00000018);

writel(0x00000001, nor_reg + 0x0000001C);

writel(0x1c020000, nor_reg + 0x00000020);

writel(0x00000000, nor_reg + 0x00000024);

writel(0x0804a240, nor_reg + 0x00000028);

writel(0x00000000, nor_reg + 0x0000002C);

}

static struct physmap_flash_data nor_flash_data = {

.probe_type = "map_rom",

.width = 2,

.parts = mxc_nor_partitions,

.nr_parts = ARRAY_SIZE(mxc_nor_partitions),

};

Step 3: I modified the boot parameters to initialize the weim-nor interface. I have attached the sabreauto_weimor.h file which contains the boot parameters.

In sabreauto_weimnor.h :

bootargs_base=setenv bootargs console=ttymxc0,115200

bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp

nfsroot=${serverip}:${nfsroot},v3,tcp

bootcmd_net=run bootargs_base bootargs_nfs; tftpboot ${loadaddr} ${kernel};

bootm

bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p1 rootwait

weim-nor video=mxcfb0:dev=ldb,640x480M@60,if=RGB666 ldb=sep0

bootcmd_mmc1=run bootargs_base bootargs_mmc; mmc dev 2; mmc read ${loadaddr}

0x800 0x2000; bootm

bootcmd=run bootcmd_mmc

bootargs_nor=setenv bootargs ${bootargs} root=/dev/mtdblock3 rw

rootfstype=jffs2 ip=none weim-nor

bootcmd_mmc=run bootargs_base bootargs_mmc; cp.l 0x8080000 ${loadaddr}

0x400000; bootm

Step 4: I then booted my board with the kernel and rootfs.

Step 5: I configured the FPGA to include a ROM mapped to the EIM bus of the processor as specified above. I used the memtool utility to read the memory from the FPGA.

$cd /

$cd unit_tests

Usage:

Read:

/unit_tests $ ./memtool <-8, -16, -32> <Physical address> <count>

You can now observe the data read from the FPGA.

I am now trying to write data to the FPGA. I will add it to this document once it is complete.

regards,

Nishad

Original Attachment has been moved to: board-mx6q_sabreauto.h.zip

Original Attachment has been moved to: board-mx6q_sabreauto.c.zip

Original Attachment has been moved to: mx6q_sabreauto_weimnor.h.zip

Re: Reading data from an FPGA connected to the iMX6q EIM bus

浩卢 — Wed, 11 May 2016 01:25:16 GMT

This is very useful for me.Tks.

Re: Reading data from an FPGA connected to the iMX6q EIM bus

hanseunglee — Thu, 02 Jun 2016 05:49:19 GMT

Thank you for your time.

It is very good for me. i also to be try emi from fpga.

i.MX ProcessorsのトピックRe: Reading data from an FPGA connected to the iMX6q EIM bus

Reading data from an FPGA connected to the iMX6q EIM bus

Re: Reading data from an FPGA connected to the iMX6q EIM bus

Re: Reading data from an FPGA connected to the iMX6q EIM bus