<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: iMX6 Bare-Metal SMP Debugging using DS-5 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297235#M37026</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jonathan&lt;/P&gt;&lt;P&gt;by default cores 1-3 are disabled, there is special procedure to&lt;/P&gt;&lt;P&gt;run them. Please look at description and example codes in SDK&lt;/P&gt;&lt;P&gt;Chapter 3 Multicore Startup.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"MX6_PLATFORM_SDK "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 16 Apr 2014 07:39:23 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2014-04-16T07:39:23Z</dc:date>
    <item>
      <title>iMX6 Bare-Metal SMP Debugging using DS-5</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297234#M37025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Contrary to the multiple cpus I've used with DS-5 the iMX6Q always shows core 1-3 as being powered down. Anyone been able to get DS-5 to connect to all four cores?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For reference I'm using the iMX6 SABRE dev board and DS-5 5.18 pro.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jonathan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Apr 2014 19:52:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297234#M37025</guid>
      <dc:creator>jonathanblancha</dc:creator>
      <dc:date>2014-04-15T19:52:13Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Bare-Metal SMP Debugging using DS-5</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297235#M37026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jonathan&lt;/P&gt;&lt;P&gt;by default cores 1-3 are disabled, there is special procedure to&lt;/P&gt;&lt;P&gt;run them. Please look at description and example codes in SDK&lt;/P&gt;&lt;P&gt;Chapter 3 Multicore Startup.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"MX6_PLATFORM_SDK "&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&amp;amp;nodeId=018rH3ZrDRB24A&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Apr 2014 07:39:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297235#M37026</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2014-04-16T07:39:23Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Bare-Metal SMP Debugging using DS-5</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297236#M37027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi again,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As a reference for anyone else trying to do the same thing powering up the cores after the debug session is started won't enable debugging on those cores meaning that breakpoints and semi hosting won't work. Recommended approach is to let a bootloader or a debug script do the multi core init.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jonathan Blanchard&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 01 May 2014 14:18:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Bare-Metal-SMP-Debugging-using-DS-5/m-p/297236#M37027</guid>
      <dc:creator>jonathanblancha</dc:creator>
      <dc:date>2014-05-01T14:18:59Z</dc:date>
    </item>
  </channel>
</rss>

