topic Re: PCIe REFCLK in i.MX Processors

PCIe REFCLK

danielkubiak — Tue, 15 Apr 2014 16:22:49 GMT

Hello,

I'm looking for information about the CLK1_N and CLK1_P outputs of IMX6 device:

These outputs are used as PCIe REFCLK.

In the IMX6 hardware development guide (IMX6DQ6DLHDG) table 2-10 PCIe recommendations, It is recommended to place the termination resistors close to the receiver.

In addition, the clocks are AC coupled between the IMX6 device and the PCIe connector on SPF-27147_C3 evaluation board

I would like to be sure that the clocks outputs are LVDS outputs.

Normally the clocks in PCIe application is on HCSL technology that needs terminations to be close to the source and don't need to be AC coupled between the source and the receiver.

Regards

Daniel

Re: PCIe REFCLK

Yuri — Wed, 16 Apr 2014 10:34:36 GMT

You are right, external AC coupling is needed since the clocks are LVDS, but

not HCSL compatible.

Have a great day,
Yuri

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Re: PCIe REFCLK

robo — Wed, 23 Jul 2014 09:41:59 GMT

Hi Yuri,

how does the termination look like at the imx6S:

if the imx6S is a PCIe EndPoint (Add in card)
AND the Root Complex has an CML/HSCL RefCLK output?

Am I right, that all the recommendations for the RefCLK (DataSheet/HW manual/Ref-Designs) are LVDS to LVDS based?

Regards

Re: PCIe REFCLK

Yuri — Mon, 28 Jul 2014 06:19:12 GMT

Appears, You are right, our recommendations are LVDS based, and - sorry - we do not
provide specific ones for other configurations.

Re: PCIe REFCLK

robo — Mon, 28 Jul 2014 16:20:04 GMT

Hi Yuri,

thanks for your answer and to clarify this topic.

But btw, this should be added as a note to the RefManual/HW Datasheet.

The topic opener shall account, that the common mode voltage disappears after the AC couple capacitors. Hence, from my point of view, this must be re-added "behind" the capacitors to full-fill the TIA/EIA-644A standard. Or he has to remove these capacitors. In the mentioned schematic the pull-down resistors "after" the capacitors shall reduce EMI. That means, if no card is inserted, the circuit is terminated. If a PCIe card is inserted (and an additional termination is on the Add-In card) this would destroy the RefCLK signal levels -> two 50Rs are attached in parallel. If the imx has an LVDS output (3.5mA) -> The v_diff will set 0.175V, which is quite to less for a LVDS input stage. That means on the PCIe add in card there is no termination allowed. But unfortunately some LVDS inputs has them internal.

But nevertheless, as long as the most PCIe RefCLK in/outs are HCSL based, a signal level adaption has to be accounted at any time.

Regards

Re: PCIe REFCLK

Yuri — Wed, 12 Nov 2014 09:37:22 GMT

HW Design Checking List for i.Mx6DQSDL Rev2.8 conatins useful recommendations

about PCIe clock :

"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification.

For PCIe Gen1 application, following low cost soultion can be used(DC bias and AC

impedance should be considered). Please refer to "HW Design Checking List for i.Mx6DQSDL

Rev2.7.xlsx", sheet "Schematic", Ref12 for more info."

"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe

Gen2 compliance test. Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL

outputs solution. One clock channel connect to i.MX6 as a reference input, please click

Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev2.7.xlsx") for reference circuit.

Another clock channel should connect to PCIe connector, please contact generator vendor

for detailed design guide."

https://community.freescale.com/docs/DOC-93819

Re: PCIe REFCLK

timharvey — Thu, 16 Apr 2015 20:30:21 GMT

Yuri,

I noticed recently that while the IMX6SX-SabreSD reference implements the circuit from Ref12 in the hw design checklist which has series caps to AC couple, 470ohm pull-ups and 56ohm pull-downs to load and DC bias. Why exactly is this not Gen 3 compliant and what does that imply? Does this mean a Gen3 device may fail instead of stepping down to Gen2?

What are the implications of using the circuit from the original SabreSD reference design which has series caps to AC couple, and 50ohm pull-downs for loading (but fails to DC bias). I would think that while this may work fine with PCIe devices that apply their own DC bias to the clock, it would completely fail to link on other devices that do not. Is this correct?

Regards,

Tim

KevinWong

partner

gateworks

Re: PCIe REFCLK

Yuri — Fri, 17 Apr 2015 03:58:49 GMT

Tim, hello !

Please follow the IMX6SX-SabreSD reference design while i.MX6SX Design Checklist is not published.

Regards,

Yuri.

Re: PCIe REFCLK

timharvey — Wed, 29 Apr 2015 23:08:51 GMT

Yuri,

Understood, but if I follow the IMX6SX-SabreSD reference design can you please explain what about that circuit makes you say the clock fail Gen2 compliance testing. Is it the jitter? I can find no reference in the IMX6 datasheet or reference manual as to the accuracy of the LVDS clock outputs. The translation circuit in the ref design should produce a 400mV pk-to-pk clock DC biased at ~350mV which from my understanding should be appropriate voltage levels and swing for the PCIe clock for both Gen1 and Gen2.

Thanks,

Tim

Re: PCIe REFCLK

Yuri — Tue, 05 May 2015 05:57:38 GMT

Please look at my comments below.

1.

> … can you please explain what about that circuit makes you say the clock fail
> Gen2 compliance testing. Is it the jitter?

Yes, we may find the following note on sheet 16 of i.MX6 SoloX design :

“All components in this block are needed to be populated for PCIe GEN2 clock

jitter test”.

2.
> I can find no reference in the IMX6 datasheet or reference manual as to the
> accuracy of the LVDS clock outputs.

From i.MX6 Datasheet(s) regarding CLK1_P/N signals :
“See LVDS pad electrical specification for further details”.

LVDS specs link :

http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/2848/1/LVDS.pdf

Regards,

Yuri.

Re: PCIe REFCLK

timharvey — Wed, 06 May 2015 16:08:03 GMT

Yuri,

Thanks for the info. I still can not find any specification as to the accuracy of the LVDS clock output of the IMX CLK1_P/N signals. Obviously Freescale knows this information because you are saying it doesn't pass the Gen2 compliance test. I understand that the jitter on the board would of course be layout/design related, but there must be a spec that states the accuracy of the IMX6's internal LVDS clock somewhere?

Regards,

Tim

Re: PCIe REFCLK

Yuri — Tue, 12 May 2015 07:16:02 GMT

Please use the LVDS specs about clock accuracy.

Regards,

Yuri.

Re: PCIe REFCLK

cblack — Wed, 14 Sep 2016 16:12:22 GMT

Without patch https://patchwork.kernel.org/patch/8767131/ could this cause the "phy link never came up" error? Or, would this GEN2 noncompliance not affect the link up?

thanks