Pulse width between two chip select of SPI

daweiyou — Thu, 13 Mar 2014 14:13:57 GMT

Hi Guys:

Here are question for Pulse width between two chip select of SPI, i.MX6

The Wait States between two Chip Select (SS) signals can be decided

by ECSPI_PERIODREG[SAMPLE_PERIOD], but even if SAMPLE_PERIOD is 0,

the wait width still exist, from datasheet, the Min of "CS4 ECSPIx_SSx pulse width", tCSLH , is Half ECSPIx_SCLK period,

but Max is not defined.

So could you tell me what's the Max value and how to adjust it?

Actually, by testing, the actual value is almost 1us, if I want to reduce it, how can I do? thx

Re: Pulse width between two chip select of SPI

YixingKong — Fri, 13 Jun 2014 08:56:29 GMT

Dawei

We are sorry for getting back to you so late. Are you still stuck with the issue? If you have somehow resolved the issue, can we close the discussion? If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

topic Pulse width between two chip select of SPI in i.MX Processors

Pulse width between two chip select of SPI

Re: Pulse width between two chip select of SPI