topic i.MX6SDL RGMII Tr/Tf. in i.MX Processors

i.MX6SDL RGMII Tr/Tf.

satoshishimoda — Mon, 12 May 2014 08:57:15 GMT

Hi community,

I want to confirm about i.MX6SDL RGMII spec.

Please see Table 64 in IMX6SDCEC Rev.3, Tr/Tf are defined in this table.

Our partner guess these specs are difined when i.MX6 is TX because deive strength is mentioned in foot not No.1.

Then, how about when i.MX6 is RX?

Should all signals (clk, ctl, data, etc) satisfy thes RGMII specs?

Best Regards,

Satoshi Shimoda

Re: i.MX6SDL RGMII Tr/Tf.

Yuri — Tue, 13 May 2014 10:51:42 GMT

RGMII Tr/Tf relate to clock rise / fall times (at transmitter) .

Have a great day,
Yuri

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Re: i.MX6SDL RGMII Tr/Tf.

satoshishimoda — Wed, 14 May 2014 01:44:49 GMT

Hi Yuri,

According to your reply, there is no restriction about Tr/Tf of RGMII receiver, right?

Best Regards,

Satoshi Shimoda

Re: i.MX6SDL RGMII Tr/Tf.

Yuri — Wed, 14 May 2014 09:55:18 GMT

There are no restrictions for edges for receiver side as much as the transceiver
side meets the Tr / Tf requirements and

TskewT max of MAC is less than TskewR min of PHY ;

TskewT max of PHY is less than TskewR min of MAC.

Also PC board design clocks should be routed such that an additional trace

delay of greater than 1.5 ns and less than 2.0 ns will be added to the

associated clock signal.

Have a great day,
Yuri