topic Re: [imx6] PLLv3 clock change in i.MX Processors

[imx6] PLLv3 clock change

jiadawang — Mon, 12 May 2014 07:44:32 GMT

According to User manual

section 18.5.1.5.3 PLL clock change

- "Before changing the PLL setting, power it down. Power up the PLL after the change"

But currently neither 3.10 FSL BSP

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-imx/clk-pllv3.c?h=imx_3.10.17_1.0.0_ga

nor 3.15 mainline kernel

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-imx/clk-pllv3.c?id=refs/tags/v3.15-rc5

is doing power down/up when changing of PLL clock rate in set_rate() interface.

I do find one patch from Russell King

[134/222] ARM: imx: keep PLLs in bypass while they're locking - Patchwork

in this patch PLL is set to bypass mode before change its rate

my question is:

what is the proper operation to change PLL rate? should pllv3 driver power down/up PLL clock just as user manual stated.

If pllv3 driver keeps current behavior (directly change clock rate with out power down/up or set it to bypass mode),

is there any potential problem, like clock glitch?

Thanks,

Jiada

Re: [imx6] PLLv3 clock change

gusarambula — Mon, 12 May 2014 19:33:02 GMT

Please follow the procedure as mentioned on the Reference Manual as this is the correct way in order to ensure a robust operation of the processor.

In the case of our BSP a software reset is required after setting the new PLL rate, that’s why a PLL power down/up does not appear in the code.

While bypassing the PLL is theoretically possible, behavior using this method cannot be guaranteed.

Re: [imx6] PLLv3 clock change

DirkBehme — Tue, 13 May 2014 05:32:41 GMT

First, many thanks for the quick answer!

As usual, I think it's essential to get the details correctly, so some more detailed questions:

1. While the question in this thread is specific to PLLv3, the answers apply to all PLLs, correct? I.e. we have to do the same for PLLv1, PLLv2 etc, correct?

2. I have some difficulty to match the section 18.5.1.5.3 PLL clock change - "Before changing the PLL setting, power it down. Power up the PLL after the change" to the register bits of the CCM_ANALOG_PLL_xxx registers. The CCM_ANALOG_PLL_xxx registers have 3 bits which seem to be involved in our discussion:

POWERDOWN
ENABLE
BYPASS

So the correct sequence to change the PLL rate is

a) Put the PLL in BYPASS by setting the BYPASS bit CCM_ANALOG_PLL_xxx[16] = 1 (or ensure in different way that the peripherals are not driven by the PLL clock we are switching, e.g. by disabling them or switching them to an other clock source)

b) Powerdown the PLL by setting the POWERDOWN bit CCM_ANALOG_PLL_xxx[12] = 1

c) Change the dividers

d) Powerup the PLL by setting the POWERDOWN bit CCM_ANALOG_PLL_xxx[12] = 0

e) Wait for lock (then the clock is stable)

f) Remove the BYPASS by setting the BYPASS bit CCM_ANALOG_PLL_xxx[16] = 0 (feed the peripherals with the new clock)

And while doing this, don't touch the ENABLE bit, i.e. keep the PLL enabled by CCM_ANALOG_PLL_xxx[13] = 1

Is this sequence correct?

3. In the recent FSL BSP the before changing the clock, the bypass is explicitly removed:

linux-2.6-imx.git - Freescale i.MX Linux Tree

Wouldn't this result in any clock glitch? Even if you reset afterwards?

Re: [imx6] PLLv3 clock change

DirkBehme — Wed, 14 May 2014 11:45:41 GMT

http://www.spinics.net/lists/arm-kernel/msg331143.html

correct?

Re: [imx6] PLLv3 clock change

karina_valencia — Thu, 15 May 2014 14:13:14 GMT

gusarambula can you continue with the follow up please?

Re: [imx6] PLLv3 clock change

gusarambula — Mon, 19 May 2014 14:11:44 GMT

Yes, the answer applies to virtually all PLLs, except for the clocks that can’t be stopped, like the core clocks.

As for the sequence it is correct.

Regarding the i.MX linux tree mentioned, this is not the official BSP but rather a modified version so while it might work, it is recommended to use the original BSP configuration.

Re: [imx6] PLLv3 clock change

norishinozaki — Wed, 11 May 2016 07:54:05 GMT

Hello,

I'd like to change PFD1_FRAC of the PLL3.

Do I need to follow the above sequence when just changing a PFD1 value?

BR.

N.S.