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    <title>topic Re: Re: SSI underrun interrupt in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162236#M3640</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The answer is located here: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-93857"&gt;https://community.freescale.com/docs/DOC-93857&lt;/A&gt;&lt;/P&gt;&lt;P&gt;"The root cause of this issue is that SSI1/3 use SDMA, and also use IPMUX, but there is not the clock dependency between SDMA and IPMUX, so sometimes IPMUX clock is closed automatically"&lt;/P&gt;&lt;P&gt;I've applied the patch and&amp;nbsp; underruns are gone.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Sep 2013 06:08:50 GMT</pubDate>
    <dc:creator>warl0rd</dc:creator>
    <dc:date>2013-09-11T06:08:50Z</dc:date>
    <item>
      <title>SSI underrun interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162234#M3638</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Default Monospace,Courier New,Courier,monospace'; font-size: 2; "&gt;Im using IMX53 with L2.6.35_11.09.01_ER_source BSP.&lt;BR /&gt;I have connected to CPU two audio codecs. First to AUDMUX4 and second to AUDMUX5. First of them uses SSI1, second SSI2.&lt;BR /&gt;&lt;BR /&gt;When i play music on SSI2-&amp;gt;AUDMUX5 everything is fine.&lt;BR /&gt;When i try on &amp;nbsp;SSI1-&amp;gt;AUDMUX4 i get a little distortion cosed propably by zeros in audio stream coming out from imx. I get errors on console like below:&lt;BR /&gt;&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=184001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=185001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=186001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=187001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=188001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=189001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=190001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=191001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=192001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=193001&lt;BR /&gt;imx_ssi_irq mxc_ssi SISR 323 SIER 180100 fifo_errs=194001&lt;BR /&gt;...&lt;BR /&gt;&lt;BR /&gt;This are interrupts from SSI1 whitch tels about fifo underrun I think.&lt;BR /&gt;Do anybody help me with this issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 21 May 2012 07:48:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162234#M3638</guid>
      <dc:creator>swroch</dc:creator>
      <dc:date>2012-05-21T07:48:16Z</dc:date>
    </item>
    <item>
      <title>Re: SSI underrun interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162235#M3639</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have almost the same case. I use AdeneoEmbedded kernel (Release 4.2). There is a SGTL5000 codec connected to SSI2 via AUDMUX5 and a GSM modem (DVI port) connected to SSI1 via AUDMUX3. Sample rate is 8kHz, 16-bit, I2S. Modem is master. Play buffer of SSI is located in IRAM. So when I start sending data and the DMA controller starts transfers, SSI reports multiple TX underruns. About 110 per 100 ms or 1600 slots&lt;/P&gt;&lt;P&gt;imx_ssi_irq mxc_ssi SISR 1a0 SIER 180100 fifo_errs=1&lt;/P&gt;&lt;P&gt;It seems that DMA controller fails to fetch data in time... What could it be??&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Sep 2013 10:29:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162235#M3639</guid>
      <dc:creator>warl0rd</dc:creator>
      <dc:date>2013-09-10T10:29:25Z</dc:date>
    </item>
    <item>
      <title>Re: Re: SSI underrun interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162236#M3640</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The answer is located here: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-93857"&gt;https://community.freescale.com/docs/DOC-93857&lt;/A&gt;&lt;/P&gt;&lt;P&gt;"The root cause of this issue is that SSI1/3 use SDMA, and also use IPMUX, but there is not the clock dependency between SDMA and IPMUX, so sometimes IPMUX clock is closed automatically"&lt;/P&gt;&lt;P&gt;I've applied the patch and&amp;nbsp; underruns are gone.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2013 06:08:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SSI-underrun-interrupt/m-p/162236#M3640</guid>
      <dc:creator>warl0rd</dc:creator>
      <dc:date>2013-09-11T06:08:50Z</dc:date>
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