topic Re: i.mx6 floating point performance and L2 cache in i.MX Processors

i.mx6 floating point performance and L2 cache

johnconover — Wed, 12 Mar 2014 20:44:54 GMT

Hi,

We have been testing our floating point algorithms (a lot of FFT's and matrix multiplies) on a i.mx6 quad (Utilite Pro.) We are considering going to a dual or

dual Lite. The clock speed reduction from 1.2Ghz to 1Ghz should be straight forward as far what to expect in the decreasing (double precision) floating point

performance. What we are not so sure about the effect of the size decrease in L2 cache(1Mb to 512kb.) Are there any published tests or knowledge from

Freescale about floating point performance related to the L2 cache size? Our algorithms are currently running between 600msecs and 750msecs and we

need to insure the we do not go over 1sec. Any help is appreciated.

Thanks,

John Conover

Re: i.mx6 floating point performance and L2 cache

johnconover — Tue, 18 Mar 2014 18:51:17 GMT

Anyone in Freescale know if there are any Floating Point operations that are effect by L2 cache size? Maybe effects on the instruction pipeline?

Thanks,

John C.

Re: i.mx6 floating point performance and L2 cache

tongchunyang — Fri, 28 Mar 2014 02:01:50 GMT

Hi John & FSL All

I have a problem about the L2 cache.

I am using iMX6Q-Sabre-SDP to confirm MMDC speed.

I am also want to know how to decrease the size of iMX6's L2 cache size or how to disable it.

Is there any method about how to do it?

In u-boot or in kernel?

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Update:

1, L2 cache(PL310) is disabled in u-boot (lowleve_init.S)

2, L2 cache(PL310) is enabled in kernel (arch/arm/mm/cache-l2x0.c)

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Thanks & Best Wishes

Tong