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    <title>topic Using RGMII compatible PHY with i.MX6 (u-boot) in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Using-RGMII-compatible-PHY-with-i-MX6-u-boot/m-p/293708#M36193</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On our board we would like to use a RGMII-PHY together with i.MX6DL.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The MAC and PHY are connected similiar to the SABRE reference board, the main difference is that the ENET_REFCLK pin which is not connected at all.&lt;/P&gt;&lt;P&gt;I assume this is OK, according to the "Hardware Development Guide" (chapter 12.3 Generating the reference clock) "the pin labeled “ENET_REF_CLK” in Figure 12-2 is only required by the full MII interface.&lt;/P&gt;&lt;P&gt;It is not used by the RMII interface."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Based on this I made further customization (compared to the "sabre-sd" board configuration):&lt;/P&gt;&lt;P&gt;* setting bit ENET_CLK_SEL in GPR1&lt;/P&gt;&lt;P&gt;* configuring (internal) ENET PLL to generate ethernet reference clock (125Mhz),&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunatelly u-boot fails to ping another host, I'm getting "TX timeout packet" error. I suppose this could be caused by missing reference clock.&lt;/P&gt;&lt;P&gt;I checked already that management interface to the PHY works but the RGMII_TXC line doesn't show any activity (during ping command).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Did anybody encounter similiar problems?&lt;/P&gt;&lt;P&gt;Is it possible to route ENET PLL to ENET_REF_CLK (internally - using IOMUX) or does it have to be routed externally (i.e. from GPIO16 or PHY generating 125Mhz)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for any feedback&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 09 Sep 2013 17:38:10 GMT</pubDate>
    <dc:creator>tomasznowak</dc:creator>
    <dc:date>2013-09-09T17:38:10Z</dc:date>
    <item>
      <title>Using RGMII compatible PHY with i.MX6 (u-boot)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Using-RGMII-compatible-PHY-with-i-MX6-u-boot/m-p/293708#M36193</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On our board we would like to use a RGMII-PHY together with i.MX6DL.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The MAC and PHY are connected similiar to the SABRE reference board, the main difference is that the ENET_REFCLK pin which is not connected at all.&lt;/P&gt;&lt;P&gt;I assume this is OK, according to the "Hardware Development Guide" (chapter 12.3 Generating the reference clock) "the pin labeled “ENET_REF_CLK” in Figure 12-2 is only required by the full MII interface.&lt;/P&gt;&lt;P&gt;It is not used by the RMII interface."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Based on this I made further customization (compared to the "sabre-sd" board configuration):&lt;/P&gt;&lt;P&gt;* setting bit ENET_CLK_SEL in GPR1&lt;/P&gt;&lt;P&gt;* configuring (internal) ENET PLL to generate ethernet reference clock (125Mhz),&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunatelly u-boot fails to ping another host, I'm getting "TX timeout packet" error. I suppose this could be caused by missing reference clock.&lt;/P&gt;&lt;P&gt;I checked already that management interface to the PHY works but the RGMII_TXC line doesn't show any activity (during ping command).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Did anybody encounter similiar problems?&lt;/P&gt;&lt;P&gt;Is it possible to route ENET PLL to ENET_REF_CLK (internally - using IOMUX) or does it have to be routed externally (i.e. from GPIO16 or PHY generating 125Mhz)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for any feedback&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Sep 2013 17:38:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Using-RGMII-compatible-PHY-with-i-MX6-u-boot/m-p/293708#M36193</guid>
      <dc:creator>tomasznowak</dc:creator>
      <dc:date>2013-09-09T17:38:10Z</dc:date>
    </item>
    <item>
      <title>Re: Using RGMII compatible PHY with i.MX6 (u-boot)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Using-RGMII-compatible-PHY-with-i-MX6-u-boot/m-p/293709#M36194</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Chapter 11 (Using the RMII Interface) of the Hardware Development Guide for &lt;/P&gt;&lt;P&gt;i.MX6 describes RMII options :&amp;nbsp; "There are two possible pins that can either &lt;/P&gt;&lt;P&gt;source or sink the reference clock: GPIO_16 and RGMII_TX_CTL."&lt;/P&gt;&lt;P&gt;&amp;nbsp; GPIO_16 is intended for RMII reference clock; ENET_REF_CLK is intended for &lt;/P&gt;&lt;P&gt;RGMII reference clock. Next, ENET_REF_CLK is input clock, that is - an external &lt;/P&gt;&lt;P&gt;source should be applied - &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;this has been &lt;/SPAN&gt;validated.&lt;/P&gt;&lt;P&gt; Note that the ENET_REF_CLK &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;input on MX6 is fed via NVCC_ENET supply rail.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt; The internal source has to be routed externally from GPIO_16 to ENET_REF_CLK.&lt;/P&gt;&lt;P&gt;So even if customers use the internal clock they would still need to bring &lt;/P&gt;&lt;P&gt;it back in on the ENET_REF_CLK pin.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Sep 2013 08:42:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Using-RGMII-compatible-PHY-with-i-MX6-u-boot/m-p/293709#M36194</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-09-16T08:42:10Z</dc:date>
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