topic About LCDIF Timing in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293190#M36043 <HTML><HEAD></HEAD><BODY><P>Hi, </P><P></P><P>I get confused about definitions of variables in Fig 33-11 and Fig 33-12 LCD Interface Signals in MPU Write/Read Mode (iMX28 RM rev2 p.2455). </P><P></P><P>1. Are the TCS and TCH refer to CMD_SETUP and CMD_HOLD in register HW_LCDIF_TIMING respectively?</P><P>2. Are the TDSR and TDHR refer to DATA_SETUP and DATA_HOLD in register HW_LCDIF_TIMING respectively?</P><P>3. Where can I find the definitions of W1, W2, and W3?</P><P></P><P>Please let me know if available, Thanks!</P><P></P><P></P><P>BR</P><P></P><P>Cheng Shi</P></BODY></HTML> Fri, 06 Sep 2013 10:24:10 GMT x10 2013-09-06T10:24:10Z About LCDIF Timing https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293190#M36043 <HTML><HEAD></HEAD><BODY><P>Hi, </P><P></P><P>I get confused about definitions of variables in Fig 33-11 and Fig 33-12 LCD Interface Signals in MPU Write/Read Mode (iMX28 RM rev2 p.2455). </P><P></P><P>1. Are the TCS and TCH refer to CMD_SETUP and CMD_HOLD in register HW_LCDIF_TIMING respectively?</P><P>2. Are the TDSR and TDHR refer to DATA_SETUP and DATA_HOLD in register HW_LCDIF_TIMING respectively?</P><P>3. Where can I find the definitions of W1, W2, and W3?</P><P></P><P>Please let me know if available, Thanks!</P><P></P><P></P><P>BR</P><P></P><P>Cheng Shi</P></BODY></HTML> Fri, 06 Sep 2013 10:24:10 GMT https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293190#M36043 x10 2013-09-06T10:24:10Z Re: About LCDIF Timing https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293191#M36044 <HTML><HEAD></HEAD><BODY><P>Hi Cheng Shi,</P><P></P><P>The answers for question 1 and 2 are yes.</P><P></P><P>TCS and TCH refer to CMD_SETUP and CMD_HOLD in register HW_LCDIF_TIMING respectively.</P><P></P><P>TDSR and TDHR refer to DATA_SETUP and DATA_HOLD in register HW_LCDIF_TIMING respectively.</P><P></P><P>W1, W2, and W3 are governed by other timings and do not need to be configured.</P><P></P><P>Thanks,</P><P>Arthur</P></BODY></HTML> Fri, 13 Sep 2013 10:24:20 GMT https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293191#M36044 arthur_lai 2013-09-13T10:24:20Z Re: About LCDIF Timing https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293192#M36045 <HTML><HEAD></HEAD><BODY><P>Thanks Arthur, </P><P></P><P>I have finished the driver of LCDIF as a parallel bus with right timing.</P><P></P><P>BR</P><P></P><P>Cheng Shi</P></BODY></HTML> Tue, 17 Sep 2013 04:20:05 GMT https://community.nxp.com/t5/i-MX-Processors/About-LCDIF-Timing/m-p/293192#M36045 x10 2013-09-17T04:20:05Z