<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Set DDR bus size to 32 bits in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289246#M34699</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok I did some tests and here are my results : I can define CONFIG_DDR_32BIT but that's works only if I change the DDR size to 512Mo. And I don't understand why ...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Why is the DDR bus size linked to the DDR size ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 31 May 2013 12:48:31 GMT</pubDate>
    <dc:creator>AlbertT</dc:creator>
    <dc:date>2013-05-31T12:48:31Z</dc:date>
    <item>
      <title>Set DDR bus size to 32 bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289242#M34695</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have an iMX6 Dual Sabre SD (&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREPLAT" title="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREPLAT"&gt;SABRE Platform for Smart Devices Based on the i.MX 6 Series Product Summary Page&lt;/A&gt;) with 1Gb of DDR3 (2*512 I guess since I see two chips on the board but I'm not sure of that) and I would like to limit the DDR bus to 32 bits instead of 64 bits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I found this : &lt;A href="https://community.nxp.com/message/322411"&gt;Re: iMX6 DualLite with Micron DDR3 (2 x MT41J128M16HA)&lt;/A&gt; so I tried to add this lines in my flash_header.S :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x83190000)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //limit to 32 bits&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x818, 0x00000000)&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Disable ODT. TEST*/&lt;/P&gt;&lt;P&gt;MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x818, 0x00000000)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I get the same time for reading my uImage in u-boot (I've added some timers there) so I guess my modifications changed nothing. So did I follow the good way to limit the DDR bus ? And how can I check if my modifications are OK ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EDIT : or should I just replace the&lt;/P&gt;&lt;P&gt;#define CONFIG_DDR_64BIT /* for DDR 64bit */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;by&lt;/P&gt;&lt;P&gt;#define CONFIG_DDR_32BIT&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 Apr 2013 12:15:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289242#M34695</guid>
      <dc:creator>AlbertT</dc:creator>
      <dc:date>2013-04-29T12:15:29Z</dc:date>
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    <item>
      <title>Re: Set DDR bus size to 32 bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289243#M34696</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I've tried this: &lt;A href="https://community.nxp.com/docs/DOC-93963"&gt;https://community.nxp.com/docs/DOC-93963&lt;/A&gt;&lt;/P&gt;&lt;P&gt;But this doesn't work either&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2013 11:03:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289243#M34696</guid>
      <dc:creator>AlbertT</dc:creator>
      <dc:date>2013-05-13T11:03:38Z</dc:date>
    </item>
    <item>
      <title>Re: Set DDR bus size to 32 bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289244#M34697</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;From &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/xiaoli.zhang"&gt;xiaoli.zhang&lt;/A&gt;:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please refer to&lt;A _jive_internal="true" data-containerid="2004" data-containertype="14" data-objectid="93963" data-objecttype="102" href="https://community.nxp.com/docs/DOC-93963"&gt;How to Create i.MX6 32bit DDR3 Script Based on 64bit DDR3 Script&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;If you changed DDR from 64bit to 32bit on MX6SabreSD Board, please note that you must reduce DDR size:&lt;/P&gt;&lt;P&gt;/*-----------------------------------------------------------------------&lt;/P&gt;&lt;P&gt; * Physical Memory Map&lt;/P&gt;&lt;P&gt; */&lt;/P&gt;&lt;P&gt;#define CONFIG_NR_DRAM_BANKS&amp;nbsp;&amp;nbsp;&amp;nbsp; 1&lt;/P&gt;&lt;P&gt;#define PHYS_SDRAM_1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CSD0_DDR_BASE_ADDR&lt;/P&gt;&lt;P&gt;#define PHYS_SDRAM_1_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (512 * 1024 * 1024)&lt;/P&gt;&lt;P&gt;#define iomem_valid_addr(addr, size) \&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (addr &amp;gt;= PHYS_SDRAM_1 &amp;amp;&amp;amp; addr &amp;lt;= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))&lt;/P&gt;&lt;P&gt; &lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;Regarding DDR performance gap, you can run some tests which require high-bandwidth. Then you can see performance gap due to bus width.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 May 2013 18:38:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289244#M34697</guid>
      <dc:creator>admin</dc:creator>
      <dc:date>2013-05-21T18:38:15Z</dc:date>
    </item>
    <item>
      <title>Re: Set DDR bus size to 32 bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289245#M34698</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your feedback. I did not change this define so I think that's why that didn't worked. Instead I used the patch that emulate a solo on a dual or quad and that seems to work well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But I will definitely try your solution ! &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 22 May 2013 07:05:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289245#M34698</guid>
      <dc:creator>AlbertT</dc:creator>
      <dc:date>2013-05-22T07:05:18Z</dc:date>
    </item>
    <item>
      <title>Re: Set DDR bus size to 32 bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289246#M34699</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok I did some tests and here are my results : I can define CONFIG_DDR_32BIT but that's works only if I change the DDR size to 512Mo. And I don't understand why ...&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Why is the DDR bus size linked to the DDR size ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 May 2013 12:48:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Set-DDR-bus-size-to-32-bits/m-p/289246#M34699</guid>
      <dc:creator>AlbertT</dc:creator>
      <dc:date>2013-05-31T12:48:31Z</dc:date>
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  </channel>
</rss>

