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    <title>topic Re: i.MX 6SoloLite with DDR3 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286847#M33922</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Schematic&amp;nbsp; you have sent to me, we wish FSL can provide the U-BOOT and Kernel patch file. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 25 Apr 2014 07:07:06 GMT</pubDate>
    <dc:creator>bpmmaster</dc:creator>
    <dc:date>2014-04-25T07:07:06Z</dc:date>
    <item>
      <title>i.MX 6SoloLite with DDR3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286845#M33920</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;/P&gt;&lt;P&gt;&amp;nbsp; I want to use i.MX 6SoloLite + DDR3 in my design, because the LPDDR2 is very&amp;nbsp; expensive， anyone has&amp;nbsp; the reference design and source code?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Feb 2014 08:06:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286845#M33920</guid>
      <dc:creator>bpmmaster</dc:creator>
      <dc:date>2014-02-10T08:06:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6SoloLite with DDR3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286846#M33921</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is this still needed ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Feb 2014 01:46:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286846#M33921</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2014-02-20T01:46:30Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6SoloLite with DDR3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286847#M33922</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Schematic&amp;nbsp; you have sent to me, we wish FSL can provide the U-BOOT and Kernel patch file. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Apr 2014 07:07:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286847#M33922</guid>
      <dc:creator>bpmmaster</dc:creator>
      <dc:date>2014-04-25T07:07:06Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6SoloLite with DDR3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286848#M33923</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We too are attempting to use DDR3 (x32 (two x16 BGA parts)) with iMX6 Solo Lite - for cost reasons.&lt;/P&gt;&lt;P&gt;We are having great difficulty in trying to route this on 6 layers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there now a Freescale reference layout for this ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Has anyone done this and succeeded ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Feb 2015 12:53:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6SoloLite-with-DDR3/m-p/286848#M33923</guid>
      <dc:creator>Richard1z</dc:creator>
      <dc:date>2015-02-18T12:53:39Z</dc:date>
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