[ LINUX, PCIe device write not seen, probably cache related ]

fabien_le_mente — Tue, 19 Nov 2013 09:20:00 GMT

Hi,

I am new in this community, please let me introduce the context.

We are developing PCIe based devices that have been tested with INTEL root

complex so far, where they are fully operational. We are evaluating ARM platforms,

esp. the IMX6 SOLO cpu. We are using a Q7 board from CONGATECH. We are

using LINUX_3_0_35 as provided by FREESCALE.

The basic tests (PCIe word based read/write from the LINUX host) work, but we

have problems when the device writes in the host memory. You can see it as a

simplified DMA operation, where only one 32 bit word is written at a particular

physical address. I checked using a PCIe analyzer that the write operation is

performed (TLP sent). Thus, everything works fine from the device point of view.

But the host does not always 'sees' the write operation. Worst, the write operation

seems buffered somewhere in the path. I can give more details, but what I strongly

suspect is that the host reads a value from the cache (L1 or L2) instead of the DDR.

I read and tried a lot of things (using volatile wherever appropriate, GCC __clear_cache

different flush operation in kernel mode ...), but it does not solve the 'problem'. Could

someone help me?

Thanks for your help,

Re: [ LINUX, PCIe device write not seen, probably cache related ]

richard_zhu — Fri, 06 Dec 2013 02:42:41 GMT

Did you get the ack dllp after the mem write tlp is issued.

Best Regards
Richard