topic Re: Issue Loading Program Image in i.MX6 NAND Boot in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/Issue-Loading-Program-Image-in-i-MX6-NAND-Boot/m-p/285361#M33484 <HTML><HEAD></HEAD><BODY><P>I figured out the problem here. It turns out that the base sabrelite configuration included with the u-boot 2013.10 distribution contains a DCD entry that turns off the GPMI NAND clocks.</P><P></P><P>The configuration for generating the IMX compatible image uses the included clocks.cfg file (in boards/freescale/sabrelite). One of the entries in this file is</P><P><SPAN style="font-size: 10pt; line-height: 1.5em;">DATA 4, CCM_CCGR4, 0x00FFF300</SPAN></P><P></P><P>When this line is executed by the boot ROM from the DCD it ends up turning off the following clocks.</P><P>-rawnand_u_gpmi_input_apb clock</P><P>-rawnand_u_gpmi_bch_input_gpmi_io</P><P>-rawnand_u_gpmi_bch_input_bch</P><P>-rawnand_u_bch_input_apb</P><P></P><P>This effectively disables any additional loading from NAND. Changing the clocks.cfg entry to</P><P>DATA 4, CCM_CCGR4, 0xFFFFF300</P><P>fixes the problem.</P></BODY></HTML> Wed, 15 Jan 2014 19:51:08 GMT scottkanowitz 2014-01-15T19:51:08Z Issue Loading Program Image in i.MX6 NAND Boot https://community.nxp.com/t5/i-MX-Processors/Issue-Loading-Program-Image-in-i-MX6-NAND-Boot/m-p/285360#M33483 <HTML><HEAD></HEAD><BODY><P>I’m setting up a board using an i.MX6Q to boot from NAND. I have the board booting fine from an SD card using a custom u-boot image packaged with the mkimage utility into an imx boot format (IVT and DCD added to the head).</P><P></P><P>When I burn this image to NAND using the kobs-ng tool in Linux I can’t get the board to load and execute U-Boot. Using JTAG I’m able to see that the boot ROM gets to the point of loading the IVT, Boot Data and DCD and actually executing the commands in the DCD (all the MMDC values are programmed and the IVT and DCD are present in DRAM). However, the actual program binary for U-Boot is not loaded.</P><P></P><P>I’m assuming since I got to the point of loading and executing the DCD that the FCB and DBBT are good and the NAND boot is functional. Additionally, I verified that the ROM is not reading garbage data out of NAND because I can modify the values at the program destination address and they remain unchanged following a reset.</P><P></P><P>What am I missing that is preventing the final step of loading and executing the image? If the SD card boot process succeeds with the u-boot image why wouldn’t the NAND boot process?</P></BODY></HTML> Fri, 03 Jan 2014 19:12:18 GMT https://community.nxp.com/t5/i-MX-Processors/Issue-Loading-Program-Image-in-i-MX6-NAND-Boot/m-p/285360#M33483 scottkanowitz 2014-01-03T19:12:18Z Re: Issue Loading Program Image in i.MX6 NAND Boot https://community.nxp.com/t5/i-MX-Processors/Issue-Loading-Program-Image-in-i-MX6-NAND-Boot/m-p/285361#M33484 <HTML><HEAD></HEAD><BODY><P>I figured out the problem here. It turns out that the base sabrelite configuration included with the u-boot 2013.10 distribution contains a DCD entry that turns off the GPMI NAND clocks.</P><P></P><P>The configuration for generating the IMX compatible image uses the included clocks.cfg file (in boards/freescale/sabrelite). One of the entries in this file is</P><P><SPAN style="font-size: 10pt; line-height: 1.5em;">DATA 4, CCM_CCGR4, 0x00FFF300</SPAN></P><P></P><P>When this line is executed by the boot ROM from the DCD it ends up turning off the following clocks.</P><P>-rawnand_u_gpmi_input_apb clock</P><P>-rawnand_u_gpmi_bch_input_gpmi_io</P><P>-rawnand_u_gpmi_bch_input_bch</P><P>-rawnand_u_bch_input_apb</P><P></P><P>This effectively disables any additional loading from NAND. Changing the clocks.cfg entry to</P><P>DATA 4, CCM_CCGR4, 0xFFFFF300</P><P>fixes the problem.</P></BODY></HTML> Wed, 15 Jan 2014 19:51:08 GMT https://community.nxp.com/t5/i-MX-Processors/Issue-Loading-Program-Image-in-i-MX6-NAND-Boot/m-p/285361#M33484 scottkanowitz 2014-01-15T19:51:08Z