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    <title>i.MX Processors中的主题 Re: MMDC setting in flash_header.S for SABER-SDP</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284997#M33387</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I believe I can help in the question1. &lt;/P&gt;&lt;P&gt;You have to keep in mind that the DDR address starts at 0x1000_0000. So if you want a rage of 512MB you have to consider that offset.&lt;/P&gt;&lt;P&gt;The MDASP register represents the last address of CS0. That means that the last address must be 0x1000_0000+ 512MB = 0x2FFF_FFFF. &lt;/P&gt;&lt;P&gt;Which corresponds to 0x17 in the MDASP register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I will delve into the second question.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope that helps,&lt;/P&gt;&lt;P&gt;Alejandro&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 24 Mar 2014 15:32:22 GMT</pubDate>
    <dc:creator>alejandrolozan1</dc:creator>
    <dc:date>2014-03-24T15:32:22Z</dc:date>
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      <title>MMDC setting in flash_header.S for SABER-SDP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284996#M33386</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have some questions about a MMDC setup in flash_header.S for SABER-SDP. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;lt;Question 1&amp;gt;&lt;BR /&gt;For the MMDCx_MDASP setting&lt;BR /&gt;In flash_header.S, these are set up as follows.&lt;BR /&gt; - 32bit : 4Gb for CS0(2Gb DDR3 x2) =&amp;gt; MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x040, 0x00000017)&lt;BR /&gt; - 64bit : 8Gb for CS0(2Gb DDR x4) =&amp;gt; MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)&lt;/P&gt;&lt;P&gt;However, according to MMDCx_MDASP field descriptions of a reference manual, the following is explained. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;000_0000 256Mb&lt;BR /&gt;000_0001 512Mb&lt;BR /&gt;001_1111 8Gb (1GB)&lt;BR /&gt;011_1111 16Gb (2GB) - default&lt;BR /&gt;111_1111 32Gb (4GB)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think that if CS0 is used 4Gb(2Gb DDR3 x2) with 32bit, MMDCx_MDASP setting is 0x0000000F.&lt;BR /&gt;Why is MMDCx_MDASP set as 0x00000017? &lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&amp;lt;Question 2&amp;gt;&lt;BR /&gt;For the MMDCx_MAPSR setting&lt;BR /&gt;In flash_header.S, these are set up as follows.&lt;BR /&gt; - 32bit : MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)&lt;BR /&gt; - 64bit : MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)&lt;/P&gt;&lt;P&gt;However, according to MMDCx_MAPSR field descriptions of a reference manual, bit19-16 and bit3-1 fields are "Reserved".&lt;/P&gt;&lt;P&gt;Would you teach the reason written in the Reserved domain?&lt;BR /&gt;Are these fields for Freescale factories?&lt;BR /&gt;Does the user need to write a value in these Fields?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 08:38:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284996#M33386</guid>
      <dc:creator>yuuki</dc:creator>
      <dc:date>2014-03-10T08:38:08Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC setting in flash_header.S for SABER-SDP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284997#M33387</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I believe I can help in the question1. &lt;/P&gt;&lt;P&gt;You have to keep in mind that the DDR address starts at 0x1000_0000. So if you want a rage of 512MB you have to consider that offset.&lt;/P&gt;&lt;P&gt;The MDASP register represents the last address of CS0. That means that the last address must be 0x1000_0000+ 512MB = 0x2FFF_FFFF. &lt;/P&gt;&lt;P&gt;Which corresponds to 0x17 in the MDASP register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I will delve into the second question.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope that helps,&lt;/P&gt;&lt;P&gt;Alejandro&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Mar 2014 15:32:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284997#M33387</guid>
      <dc:creator>alejandrolozan1</dc:creator>
      <dc:date>2014-03-24T15:32:22Z</dc:date>
    </item>
    <item>
      <title>Re: MMDC setting in flash_header.S for SABER-SDP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284998#M33388</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have not found any information in regards the second question.&lt;/P&gt;&lt;P&gt;One thing we can try is to modify those values to the reset state, that should not affect the original behavior.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Alejandro&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Mar 2014 14:40:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MMDC-setting-in-flash-header-S-for-SABER-SDP/m-p/284998#M33388</guid>
      <dc:creator>alejandrolozan1</dc:creator>
      <dc:date>2014-03-27T14:40:37Z</dc:date>
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