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    <title>topic Re: BSP-bugs in pin routing for LCD parallel interface in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283759#M33110</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Tomasz,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you, let me talk about this with our experts so the correction can be made if needed.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 17 Dec 2013 17:36:09 GMT</pubDate>
    <dc:creator>SergioSolis</dc:creator>
    <dc:date>2013-12-17T17:36:09Z</dc:date>
    <item>
      <title>BSP-bugs in pin routing for LCD parallel interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283758#M33109</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm integrating imx6dl with an LCD (over parallel interface). The problem I encountered were some strange graphical artifacts on the display (blue points etc...).&lt;/P&gt;&lt;P&gt;Further investigation led to concusion that the pad control configuration for some pins of the interface is inproper (should be MX6DL_DISP_PAD_CTL)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please correct it in the next BSP release.&lt;/P&gt;&lt;P&gt;Affected file: arch/arm/plat-mxc/include/mach/iomux-mx6dl.h&lt;/P&gt;&lt;P&gt;Affected macros: MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 and MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best greetings&lt;/P&gt;&lt;P&gt;Tomasz Nowak&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Oct 2013 11:53:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283758#M33109</guid>
      <dc:creator>tomasznowak</dc:creator>
      <dc:date>2013-10-16T11:53:12Z</dc:date>
    </item>
    <item>
      <title>Re: BSP-bugs in pin routing for LCD parallel interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283759#M33110</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Tomasz,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you, let me talk about this with our experts so the correction can be made if needed.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Dec 2013 17:36:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283759#M33110</guid>
      <dc:creator>SergioSolis</dc:creator>
      <dc:date>2013-12-17T17:36:09Z</dc:date>
    </item>
    <item>
      <title>Re: BSP-bugs in pin routing for LCD parallel interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283760#M33111</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have performed a frammebuffer test and the colors seem to be correct. Besides we can see activity on both nets using a probe. Just in case we're going to modify the macros. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks Tomasz.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Dec 2013 09:24:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/BSP-bugs-in-pin-routing-for-LCD-parallel-interface/m-p/283760#M33111</guid>
      <dc:creator>EgleTeam</dc:creator>
      <dc:date>2013-12-19T09:24:11Z</dc:date>
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