<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic IMX536 current requirement failure &amp; Power on sequence query in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX536-current-requirement-failure-Power-on-sequence-query/m-p/282070#M32672</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are designing a board for industrial application with maximum temperature of 85C, based on&amp;nbsp; IMX536 processor in our design with PMIC 34709.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But there is a problem regarding current requirement, VGEN2(2.5V) Rail of PMIC is connected to&amp;nbsp; VDD_REG of IMX53.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The current required by IMX53's VDD_REG rail [it powers&amp;nbsp; VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) also] is 325mA and current provided by PMIC's VGEN2 rail 250mA which is less,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;How is it possible?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So,we are&amp;nbsp; powering&amp;nbsp; VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) externally from VUSB2 LDO(2.5V) of PMIC, is it possible to do so? This has not been implemented any where. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Will it affect USB usage in our case as we are planning to use USB also ?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there any power up sequence required for rails "VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V)" ?&lt;/LI&gt;&lt;/UL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 19 Jul 2013 10:36:06 GMT</pubDate>
    <dc:creator>neerajshukla</dc:creator>
    <dc:date>2013-07-19T10:36:06Z</dc:date>
    <item>
      <title>IMX536 current requirement failure &amp; Power on sequence query</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX536-current-requirement-failure-Power-on-sequence-query/m-p/282070#M32672</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are designing a board for industrial application with maximum temperature of 85C, based on&amp;nbsp; IMX536 processor in our design with PMIC 34709.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But there is a problem regarding current requirement, VGEN2(2.5V) Rail of PMIC is connected to&amp;nbsp; VDD_REG of IMX53.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The current required by IMX53's VDD_REG rail [it powers&amp;nbsp; VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) also] is 325mA and current provided by PMIC's VGEN2 rail 250mA which is less,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;How is it possible?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So,we are&amp;nbsp; powering&amp;nbsp; VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) externally from VUSB2 LDO(2.5V) of PMIC, is it possible to do so? This has not been implemented any where. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Will it affect USB usage in our case as we are planning to use USB also ?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there any power up sequence required for rails "VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V)" ?&lt;/LI&gt;&lt;/UL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 19 Jul 2013 10:36:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX536-current-requirement-failure-Power-on-sequence-query/m-p/282070#M32672</guid>
      <dc:creator>neerajshukla</dc:creator>
      <dc:date>2013-07-19T10:36:06Z</dc:date>
    </item>
    <item>
      <title>Re: IMX536 current requirement failure &amp; Power on sequence query</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX536-current-requirement-failure-Power-on-sequence-query/m-p/282071#M32673</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;OL style="list-style-type: decimal;"&gt;&lt;LI&gt;&lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; 325mA in Table 9 "Maximal Supply Currents" of the i.MX53 Datasheet (IMX53AEC, Rev. 5, 12/2012) is given for the worst conditions, assuming VDDA and VDDAL1 are driven by the VDD_DIG_PLL (produced from VDD_REG). Please refer to footnote 4 to Table 7 "i.MX53xA Operating Ranges": "VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections."&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me remind, according to section 4.9 (Integrated LDO Voltage Regulators Parameters): "The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage regulator (default case). In this case &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; is used as internal regulator’s power source. The regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So max. &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; 325 mA includes at least VDDA + VDDAL1 max.100mA.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;On i.MX53 QSB schematic (with the PMIC 34708) VDDA + VDDAL1 are not connected to VDD_DIG_PLL (and not consumes max.100mA from VDD_REG), they are connected to VGEN1. For such connection &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; max current consumption may be estimated as (325mA - 100mA) = 225mA, sufficient for VGEN2 of PMIC 34708.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please note that Table 9 "Maximal Supply Currents" gives max. currents for worst conditions, typical values are less. For &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; typical current please refer to application note AN4271 (Rev. 0, 7/2011) "i.MX53 Supply Current Measurements on MCIMX53SMD Board"&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;lt; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="http://www.freescale.com/files/32bit/doc/app_note/AN4270.pdf"&gt;http://www.freescale.com/files/32bit/doc/app_note/AN4270.pdf&lt;/A&gt;&lt;SPAN&gt; &amp;gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;2. Recommended power supply solutions may be found in Chapter 5 (Setup Power Management) of “i.MX53 System Development User’s Guide”. Please pay attention on erratum ERR007080 (LDO: On-chip LDO regulators may not enable or have a delayed output on power up).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;lt; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="http://cache.freescale.com/files/32bit/doc/errata/IMX53CE.pdf"&gt;http://cache.freescale.com/files/32bit/doc/errata/IMX53CE.pdf&lt;/A&gt;&lt;SPAN&gt; &amp;gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;VDD_ANA_PLL and VDD_DIG_PLL may be powered externally (with proper voltages).&lt;/P&gt;&lt;P&gt;As for power up sequence please take a look at section 4.2.1 (Power-Up Sequence) of the Datasheet: “If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage during the power-up, it is recommended to activate the &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; before or at the same time with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V &lt;STRONG&gt;VDD_REG&lt;/STRONG&gt; supply shut-off output impedance is higher than 1 kOhm when it is inactive.”&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Aug 2013 20:20:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX536-current-requirement-failure-Power-on-sequence-query/m-p/282071#M32673</guid>
      <dc:creator>reyes</dc:creator>
      <dc:date>2013-08-12T20:20:47Z</dc:date>
    </item>
  </channel>
</rss>

