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    <title>topic Re: spi nor flash boot in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281547#M32520</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Xiaoqiang,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;IMX6 can support&amp;nbsp; spi nor boot with BOOT_CFG1[7:4] = 0000.&lt;/P&gt;&lt;P&gt;But Current SD board uses KEY relative PINs as&lt;/P&gt;&lt;P&gt;SPI interface. However, this set of PINs are not&lt;/P&gt;&lt;P&gt;supported by ROM. Therefore, SPI NOR boot is&lt;/P&gt;&lt;P&gt;not supported by Smart Device Board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can check the Sabre-AI board for reference. Sabre-AI board supports SPI NOR boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Biyong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 30 Dec 2013 11:50:14 GMT</pubDate>
    <dc:creator>BiyongSUN</dc:creator>
    <dc:date>2013-12-30T11:50:14Z</dc:date>
    <item>
      <title>spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281546#M32519</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am working on  i.MX6 SABRE-SD board and want to boot from spi nor flash. But the guide doesn't mention this way. Now I wonder if it supports this way.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Anyone can help me? Thanks in advance!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Xiaoqiang&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Dec 2013 09:11:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281546#M32519</guid>
      <dc:creator>xiaoqiangyang</dc:creator>
      <dc:date>2013-12-30T09:11:19Z</dc:date>
    </item>
    <item>
      <title>Re: spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281547#M32520</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Xiaoqiang,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;IMX6 can support&amp;nbsp; spi nor boot with BOOT_CFG1[7:4] = 0000.&lt;/P&gt;&lt;P&gt;But Current SD board uses KEY relative PINs as&lt;/P&gt;&lt;P&gt;SPI interface. However, this set of PINs are not&lt;/P&gt;&lt;P&gt;supported by ROM. Therefore, SPI NOR boot is&lt;/P&gt;&lt;P&gt;not supported by Smart Device Board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can check the Sabre-AI board for reference. Sabre-AI board supports SPI NOR boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Biyong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Dec 2013 11:50:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281547#M32520</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2013-12-30T11:50:14Z</dc:date>
    </item>
    <item>
      <title>Re: spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281548#M32521</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Biyong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your explanation. As you said，the IMX6&amp;nbsp; processor supports SPI NOR boot but the&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt; &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 12.800000190734863px;"&gt;Smart Device Board&lt;/SPAN&gt;&amp;nbsp; can not. If I &lt;/SPAN&gt;desing my own board, I can add SPI NOR boot to my design, right?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Dec 2013 01:07:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281548#M32521</guid>
      <dc:creator>xiaoqiangyang</dc:creator>
      <dc:date>2013-12-31T01:07:26Z</dc:date>
    </item>
    <item>
      <title>Re: spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281549#M32522</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp; Biyong,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; now i want to&amp;nbsp; design one board use SPI NOR boot&amp;nbsp; similar to Sbare-AI board,EIM pin that i have used. the pin i use is diffrent from Sbare-AI board,so i want to do some modify on linux which run in ram,can you tell me some idea about this? Thank you !&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Dec 2013 05:31:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281549#M32522</guid>
      <dc:creator>caoping</dc:creator>
      <dc:date>2013-12-31T05:31:27Z</dc:date>
    </item>
    <item>
      <title>Re: spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281550#M32523</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Xiaoqiang,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Correct. You can add the SPI-NOR boot to your board as Sabre-AI does. You can compare&amp;nbsp; Sabre-AI board to Sabre-SD board to find the differences.&lt;/P&gt;&lt;P&gt;Those differences are what you need to do on your board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Biyong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jan 2014 05:16:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281550#M32523</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2014-01-03T05:16:45Z</dc:date>
    </item>
    <item>
      <title>Re: spi nor flash boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281551#M32524</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Cao ping,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the imx6q reference manual:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Serial ROM through SPI and I2C--&amp;gt;Serial ROM eFUSE Configuration&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; -&amp;gt;ECSPI Boot&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; --&amp;gt; ECSPI IOMUX Pin Configuration&lt;/P&gt;&lt;P&gt;After you have read the referece manual, let take the AI board hardware as an example:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI_NOR 0 0 1 1 x x x x x x x x x x x x 0 0 0 0 0 0 0 0 x x 0 1 1 0 0 0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BT_CFG1_=0011xxxx&lt;/P&gt;&lt;P&gt;BT_CFG4_=xx011000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to Table 8-22. Serial ROM Boot eFUSE Descriptions&lt;/P&gt;&lt;P&gt;BT_CFG1:&amp;nbsp;&amp;nbsp;&amp;nbsp; 0011&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Boot from Serial ROM&lt;/P&gt;&lt;P&gt;BT_CFG4:&amp;nbsp;&amp;nbsp;&amp;nbsp; xx011000:&lt;/P&gt;&lt;P&gt;BOOT_CFG4[5:4]=01&amp;nbsp;&amp;nbsp; CS select (SPI only) 01 - ECSPIx_SS1&lt;/P&gt;&lt;P&gt;BOOT_CFG4[3] =1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1 - 3-bytes (24-bit)&lt;/P&gt;&lt;P&gt;BOOT_CFG4[2:0]=000 -&amp;nbsp; ECSPI-1&lt;/P&gt;&lt;P&gt;According to Table 8-25. SPI IOMUX Pin Configuration, the pins are:&lt;/P&gt;&lt;P&gt;MISO&amp;nbsp;&amp;nbsp; EIM_D17.alt1, MOSI&amp;nbsp;&amp;nbsp; EIM_D18.alt1, SS1 EIM_D19.alt1, SCLK EIM_D16.alt1&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then you can check the schematics of AI board whether it is our expectation.&lt;/P&gt;&lt;P&gt;Yes, it is.&lt;/P&gt;&lt;P&gt;So, you can use ECSPI-1 ECSPI-2 ECSPI-3 ECSPI4 ECSPI-5 for SPI boot.&lt;/P&gt;&lt;P&gt;But please make use on collisions happen. &lt;/P&gt;&lt;P&gt;You can use the iomux tool to do the check. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Biyong&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Biyong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jan 2014 06:50:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/spi-nor-flash-boot/m-p/281551#M32524</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2014-01-03T06:50:23Z</dc:date>
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