i.MX ProcessorsのトピックRe: Enable Hardware Counters on PL310 L2 Cache

Enable Hardware Counters on PL310 L2 Cache

tarteauxfraises — Wed, 28 Aug 2013 12:41:38 GMT

Hi,

I'm trying to enable PL310 L2 Cache event monitoring on i.MX6 sabrelite and i get zeroed out PMU counters. The "CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual" part "2.5.8 Cache event monitoring" says "When the signal on the SPNIDEN pin is LOW the event bus and event counters only output or count non-secure events.". I'm reading SPNIDEN value using Debug Control Register and i get zero.

The Cortex -A9 Technical Reference Manual (Revision: r4p1) in part "10.8.3 Changing the authentication signals" says "The NIDEN, DBGEN, SPIDEN, and SPNIDEN input signals are either tied off to some fixed value or controlled by some external device.".

I find no reference for these signals in the "i.MX 6Dual/6Quad Applications Processor Reference Manual".

It is there any way to enable input signals on the board?

Thanks,

Re: Enable Hardware Counters on PL310 L2 Cache

Yuri — Tue, 24 Dec 2013 03:12:44 GMT

You may try to configure security level register bits for ARM DAP in CSU of the i.MX6.
Please refer to Security Reference Manual for i.MX6.

https://www.freescale.com/webapp/Download?colCode=IMX6DQ6SDLSRM&appType=moderatedWithoutFAE&fpsp=1&Parent_nodeId=1337637…

Please take a look at the next thread.

"Set SPNIDEN from fuse?"

https://community.freescale.com/message/368527#368527

Set SPNIDEN from fuse?

Re: Enable Hardware Counters on PL310 L2 Cache

tarteauxfraises — Mon, 24 Mar 2014 14:26:19 GMT

Hello,

I tried, as you said, to configure the security level register bits for arm DAP. I set to 1 the b23-b16 and the bits b7-b0 of the Config security level register 29 but it does not change anything.

Does someone have already enabled L2 counters on imx6 sabrelite?

Best regards

Re: Enable Hardware Counters on PL310 L2 Cache

nicochato — Fri, 11 Jul 2014 14:20:27 GMT

Hello,

I am facing the same issue than you on my SabreLite IMX6Q board. Did you finally succeed to use event counters on PL310 ?

So far, the only L2 cache statistics that I could get are L2 data cache read and write access, using PMU events 0x50 and 0x51. (it sounds that common microarchitectural event numbers related to L2 don’t work (events 0x16, 0x17, 0x18))

Thanks

Re: Enable Hardware Counters on PL310 L2 Cache

renatomancuso — Sat, 10 Dec 2016 02:52:55 GMT

Same problem here.

I am working on a i.MX6Q, have performed the setup of the event counter registers, enabled the events and enabled the "Event monitor bus enable" bit in the Auxiliary Control Register (bit 20).

Nonetheless, the counters (DAT1 and DAT0) are always zeroed.

Any workaround for the issue?

Re: Enable Hardware Counters on PL310 L2 Cache

winfrieddobbe — Thu, 29 Jun 2017 22:08:21 GMT

I also had zero values for the PL310 performance counters, while the other counters worked fine. After I stepped through the gator.ko module with the DS-5 kernel debugger and a DSTREAM unit to make sure the PL310 counters are programmed correctly, the PL310 event counters accidently came to life.

It looks like the PL310 PMU counters are affected by i.MX6 errata ERR006259 (while the Cortex-A9 counters are not):

i.MX6 Errata nr	Title	Description	Workarounds
6259	ARM: Debug/trace functions (PMU, PTM and ETB) are disabled with absence of JTAG_TCK clock after POR	When JTAG_TCK is not toggling after power-on reset (POR), the ARM PMU, PTM, and ETB stay in their disabled states so various debug and trace functions are not available.	Provide at least 4 JTAG_TCK clock cycles following POR if the PMU, PTM and ETB functions will be used. A free-running JTAG_TCK can also be used.

So if you shortly connect DS-5 via a DSTREAM unit to your target and then disconnect again, the PL310 counters will work.