topic Re: Fail to load vivante GPU driver in i.MX Processors

Fail to load vivante GPU driver

williamtung — Thu, 28 Feb 2013 09:16:57 GMT

Hi,

We encountered a strange issue to load vivate GPU driver during power up. Here is the scenario:

1. Build the vivate GPU driver into kernel

2. Power on the solo board and the kernel stuck at infinite loop in _ResetGPU.

3. Hard reset the board and the board can pass the _ResetGPU function to complete booting

4. Hard reset at anytime before the GPU driver loading doesn't clear this failure. Ex, hard reset in Uboot or any driver/function before vivate GPU driver can't clear the failure.

5. The problem comes back when cut power to power cycle the board.

It sounds weird but it only happens to solo board not quad board. (we have both version on same layout) Does anyone see this issue before?

Thanks.

Re: Fail to load vivante GPU driver

williamtung — Wed, 06 Mar 2013 23:48:48 GMT

I traced the _ResetGPU and found the result below:

good Reset cycle:

control = 0x70900

bad Reset cycle:

control = 0xE0

Anybody knows why the register value is stuck at 0xE0?

Re: Fail to load vivante GPU driver

PrabhuSundarara — Tue, 12 Mar 2013 21:51:22 GMT

Can you provide little more information line

-Are you using linux or Android?

-Which development board sabresd or sabreai?

-What version of BSP version you are using?

- Did you see the same problem with the prebuilt image from freescale.com/

Re: Fail to load vivante GPU driver

williamtung — Thu, 14 Mar 2013 04:39:19 GMT

Hi Prabhu,

I've tried rel_imx_3.0.35_1.1.0 and imx-android-13.4.1. Both have the same GPU boot issue.

I found two methods to get through the GPU boot issue.

1. Apply LDO patch as Freescale provided.

-- This introduces new side effect which kernel keeps popping “COULD NOT SET GP VOLTAGE!!!!” error message.

-- I’d like to spend more time on this because internal LDO is a known issue and we need to apply the patch anyways.

-- I use the workaround below for one of our customer because I didn’t see wandboard.org apply the LDO patch on their solo board.

2. Workaround adding delay:

arch/arm/mach-mx6/mx6_anatop_regulator.c

static int pu_enable(struct anatop_regulator *sreg)

{

unsigned int reg, vddsoc;

int ret = 0;

/*get PU related clk to finish PU regulator power up*/

if (!get_clk) {

if (!cpu_is_mx6sl()) {

gpu3d_clk = clk_get(NULL, "gpu3d_clk");

if (IS_ERR(gpu3d_clk))

printk(KERN_ERR "%s: failed to get gpu3d_clk!\n"

, __func__);

gpu3d_shade_clk = clk_get(NULL, "gpu3d_shader_clk");

if (IS_ERR(gpu3d_shade_clk))

printk(KERN_ERR "%s: failed to get shade_clk!\n"

, __func__);

if (IS_ERR(vpu_clk))

printk(KERN_ERR "%s: failed to get vpu_clk!\n",

__func__);

}

gpu2d_clk = clk_get(NULL, "gpu2d_clk");

if (IS_ERR(gpu2d_clk))

printk(KERN_ERR "%s: failed to get gpu2d_clk!\n",

__func__);

gpu2d_axi_clk = clk_get(NULL, "gpu2d_axi_clk");

if (IS_ERR(gpu2d_axi_clk))

printk(KERN_ERR "%s: failed to get gpu2d_axi_clk!\n",

__func__);

openvg_axi_clk = clk_get(NULL, "openvg_axi_clk");

if (IS_ERR(openvg_axi_clk))

printk(KERN_ERR "%s: failed to get openvg_axi_clk!\n",

__func__);

get_clk = 1;

}

if (external_pureg) {

/*enable extern PU regulator*/

ret = regulator_enable(pu_regulator);

if (ret < 0)

printk(KERN_ERR "%s: enable pu error!\n", __func__);

} else {

/*Track the voltage of VDDPU with VDDSOC if use internal PU

*regulator.

reg = __raw_readl(ANADIG_REG_CORE);

vddsoc = reg & (ANADIG_REG_TARGET_MASK <<

ANADIG_REG2_SOC_TARGET_OFFSET);

reg &= ~(ANADIG_REG_TARGET_MASK <<

ANADIG_REG1_PU_TARGET_OFFSET);

reg |= vddsoc >> (ANADIG_REG2_SOC_TARGET_OFFSET

-ANADIG_REG1_PU_TARGET_OFFSET);

__raw_writel(reg, ANADIG_REG_CORE);

}

/* Need to wait for the regulator to come back up */

* Delay time is based on the number of 24MHz clock cycles

* programmed in the ANA_MISC2_BASE_ADDR for each

* 25mV step.

udelay(150);

/*enable gpu clock to powerup GPU right.*/

if (get_clk) {

if (!cpu_is_mx6sl()) {

clk_enable(gpu3d_clk);

clk_enable(gpu3d_shade_clk);

clk_enable(vpu_clk);

}

clk_enable(gpu2d_clk);

clk_enable(gpu2d_axi_clk);

clk_enable(openvg_axi_clk);

}

udelay(150);

/* enable power up request */

reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);

__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);

/* power up request */

reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);

__raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET);

/* Wait for the power up bit to clear */

while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2)

;

/* Enable the Brown Out detection. */

reg = __raw_readl(ANA_MISC2_BASE_ADDR);

reg |= ANADIG_ANA_MISC2_REG1_BO_EN;

__raw_writel(reg, ANA_MISC2_BASE_ADDR);

#ifndef CONFIG_MX6_INTER_LDO_BYPASS

/* Unmask the ANATOP brown out interrupt in the GPC. */

reg = __raw_readl(gpc_base + 0x14);

reg &= ~0x80000000;

__raw_writel(reg, gpc_base + 0x14);

#endif

pu_is_enabled = 1;

if (get_clk) {

if (!cpu_is_mx6sl()) {

clk_disable(gpu3d_clk);

clk_disable(gpu3d_shade_clk);

clk_disable(vpu_clk);

}

clk_disable(gpu2d_clk);

clk_disable(gpu2d_axi_clk);

clk_disable(openvg_axi_clk);

}

return 0;

}

Re: Fail to load vivante GPU driver

mtx512 — Fri, 15 Mar 2013 08:38:19 GMT

We have same issue with the LDO patch it continually reports the "“COULD NOT SET GP VOLTAGE!!!!” message. Looks the voltage cannot be set on the anatop regulator.

Is there a freescale fix for this?

Re: Fail to load vivante GPU driver

Martin1z — Mon, 18 Mar 2013 09:08:35 GMT

Same problem here. The suggested delay workaround does resolv this situation.

Re: Fail to load vivante GPU driver

lily_zhang — Mon, 18 Mar 2013 09:52:50 GMT

Please see whether the following patch has been included into your U-boot tree:

uboot-imx.git - Freescale i.MX u-boot Tree

ENGR00235821 mx6: correct work flow of PFDsrel_imx_3.0.35_1.1.1 rel_imx_3.0.35_1.1.0 imx_v2009.08_1.1.0

PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it.

Re: Fail to load vivante GPU driver

lily_zhang — Mon, 18 Mar 2013 10:30:23 GMT

Hello, William:

You mentioned after applying for FSL LDO patch, you see new error. Can you please share the patch you applied?

Re: Fail to load vivante GPU driver

mtx512 — Mon, 18 Mar 2013 13:07:13 GMT

The "COULD NOT SET GP VOLTAGE" is caused by double initialisation of the CPU regulator in the code "mx6_cpu_regulator_init(); "

Re: Fail to load vivante GPU driver

Martin1z — Mon, 18 Mar 2013 15:27:37 GMT

I have checked my u-boot and I am sure that this fix already is included in the u-boot I am currently running.

Problem remains :smileysad:.

Re: Fail to load vivante GPU driver

lily_zhang — Tue, 19 Mar 2013 01:36:47 GMT

Thanks to share the finding. We didn't reproduce the failure and not sure whether we are using the same code baseline. Can you please clarify more details bout "double initialisation of the CPU regulator in the code "mx6_cpu_regulator_init(); "?

Re: Fail to load vivante GPU driver

lily_zhang — Tue, 19 Mar 2013 01:44:40 GMT

Please apply for LDO EN patch. We will help to settle down the warning you described.

Re: Fail to load vivante GPU driver

AnsonHuang — Tue, 19 Mar 2013 02:06:21 GMT

I am interested in the "double initialization of the CPU regulator in the code "mx6_cpu_regulator_init();", can you tell me which code base do you have? And it would be great that you can post this double initialization of CPU regulator code, thanks.

Re: Fail to load vivante GPU driver

RobinGong — Tue, 19 Mar 2013 02:43:19 GMT

Hi William,

Can you share more detail information as below about your board?

1. Is there external LDO power rail for VDDARM/VDDSOC/VDDPU? If no, you have to set 'LDO_MODE_ENABLED' which mean internal anatop regulator enabled. If yes, you can use 'LDO_MODE_BYPASSED' so that bypass internal anatop regulator to reduce power number. Of course , you should provide the right external regulator name for 'gp_reg_id'/'soc_reg_id'/'pu_reg_id' and so on. You can set the LDO mode (enable_ldo_mode)in the board level file of pmic, such as arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c . The default value is "LDO_MODE_ENABLED".

2. From your information, I guess you want to use LDO BYPASS mode and there is external power rail or pmic in your board, right? If not, I think the LDO patch shouldn't cause “COULD NOT SET GP VOLTAGE!!!!”. If yes, you'd better do some change in your pmic regulator driver as what pfuze did in the patch.

Re: Fail to load vivante GPU driver

williamtung — Wed, 20 Mar 2013 00:09:10 GMT

Hi Yibin,

1. There's no external LDO on our board. I didn't set 'LDO_MODE_ENABLED' since it's enabled by default.

2. I'll re-apply the patch to a clean build and check again.

Re: Fail to load vivante GPU driver

mtx512 — Wed, 20 Mar 2013 08:24:57 GMT

We set LDO_MODE_ENABLED and use board-mx6q_hdmidongle.c but in the code it has :

#ifndef CONFIG_MX6_INTER_LDO_BYPASS

mx6_cpu_regulator_init();

#endif

This was initialising the regulator again, commenting out those lines resolves the problem.

Re: Fail to load vivante GPU driver

RobinGong — Wed, 20 Mar 2013 08:51:05 GMT

Thanks for Jas's information.

Hi, William, So the same code as Jas's in your board file?

#ifndef CONFIG_MX6_INTER_LDO_BYPASS

mx6_cpu_regulator_init();

#endif

Re: Fail to load vivante GPU driver

Martin1z — Wed, 20 Mar 2013 11:25:52 GMT

#ifndef CONFIG_MX6_INTER_LDO_BYPASS

mx6_cpu_regulator_init();

#endif

Thanks. This also was the problem in my case.

Re: Fail to load vivante GPU driver

AnsonHuang — Wed, 20 Mar 2013 13:42:14 GMT

Hi,

Please fix this issue and apply our LDO patch to see whether it fix your GPU reset issue, thanks!

Sent from my iPad

在 2013-3-20，19:26，"Martin1z" <admin@community.freescale.com<mailto:admin@community.freescale.com>> 写道：

Freescale Community<https://community.freescale.com/index.jspa>

<https://community.freescale.com/index.jspa>

Fail to load vivante GPU driver

created by Martin1z<https://community.freescale.com/people/Martin1z> in i.MX Community - View the full discussion<https://community.freescale.com/message/320374#320374>

Re: Fail to load vivante GPU driver

williamtung — Fri, 29 Mar 2013 02:02:44 GMT

Hi,

We didn't use board-mx6q_hdmidongle.c so the failure is slight different. I kind figured out the root cause: I was trying to use same source tree for both Quad and Solo board but the cpufreq.c treats "COULD NOT SET GP VOLTAGE" is different (1.1.0=> KERN_ERR, 3.0.0 => KERN_DEBUG). See below.

1.1.1 patch:

diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c

index 4cdc837..47a70d9 100755

--- a/arch/arm/plat-mxc/cpufreq.c

+++ b/arch/arm/plat-mxc/cpufreq.c

@@ -1,5 +1,5 @@

@@ -112,7 +112,6 @@ int set_cpu_freq(int freq)

printk(KERN_ERR "COULD NOT SET GP VOLTAGE!!!!\n");

goto err3;

}

- udelay(50);

}

ret = clk_set_rate(cpu_clk, freq);

if (ret != 0) {

3.0.3 patch:

diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c

index e6dc591..7687a53 100755

--- a/arch/arm/plat-mxc/cpufreq.c

+++ b/arch/arm/plat-mxc/cpufreq.c

@@ -1,5 +1,5 @@

@@ -117,7 +117,6 @@ int set_cpu_freq(int freq)

printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n");

return ret;

}

- udelay(50);

}

ret = clk_set_rate(cpu_clk, freq);

if (ret != 0) {

Is it possible to combine them into one source for both?