<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic IMX6Q/D Muxed mode 16 bit NOR Flash interface in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277565#M31275</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am designing a IMX6Q/D/DualLite custom. I want to use NOR Flash as boot device and interfacing it using EIM. I need to use it in muxed mode putting external latches so that address and data can be latched and provided to the flash. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Address Bus - Address[0:15] is muxed with data and hence needs to be latched during the address cycle.Can EIM_LBA can be used enable the latching of the address bus.Address[16:25] is not muxed and available directly and may be given directly to the flash.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Data Bus- Data[0:15] is muxed with address bus and hence needs latching during data cycle .Since databus is bidirectional the buffer needs to have that information.Can I use EIM_RW for direction and EIM_EB0 and EIM_EB1 ored in order to enable the latch. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let me know if there is any other way of implementation for 16 bit Non-multiplexed flash interface. Is there a design implementation done so that it can referred. I checked Sabre lite and other schematics and they have non muxed implementation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Raj&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 24 Dec 2013 10:46:14 GMT</pubDate>
    <dc:creator>rajniks</dc:creator>
    <dc:date>2013-12-24T10:46:14Z</dc:date>
    <item>
      <title>IMX6Q/D Muxed mode 16 bit NOR Flash interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277565#M31275</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am designing a IMX6Q/D/DualLite custom. I want to use NOR Flash as boot device and interfacing it using EIM. I need to use it in muxed mode putting external latches so that address and data can be latched and provided to the flash. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Address Bus - Address[0:15] is muxed with data and hence needs to be latched during the address cycle.Can EIM_LBA can be used enable the latching of the address bus.Address[16:25] is not muxed and available directly and may be given directly to the flash.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Data Bus- Data[0:15] is muxed with address bus and hence needs latching during data cycle .Since databus is bidirectional the buffer needs to have that information.Can I use EIM_RW for direction and EIM_EB0 and EIM_EB1 ored in order to enable the latch. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let me know if there is any other way of implementation for 16 bit Non-multiplexed flash interface. Is there a design implementation done so that it can referred. I checked Sabre lite and other schematics and they have non muxed implementation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Raj&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Dec 2013 10:46:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277565#M31275</guid>
      <dc:creator>rajniks</dc:creator>
      <dc:date>2013-12-24T10:46:14Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q/D Muxed mode 16 bit NOR Flash interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277566#M31276</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You are rigth, EIM_LBA can be used to enable the latching of the address bus.&lt;/P&gt;&lt;P&gt;EIM_RW may be used as write strobe (affected by the WEA and WEN bit fields in the Chip&lt;/P&gt;&lt;P&gt;Select Configuration Registers). &lt;/P&gt;&lt;P&gt;EIM_OE may be used as read strobe (affected by the OEA and OEN bit fields in the Chip Select&lt;/P&gt;&lt;P&gt;Configuration Registers).&lt;/P&gt;&lt;P&gt;EIM_EB0 and EIM_EB1 may be used for byte selection. &lt;BR /&gt;Please refer to Table 22-2 (EIM External Signals) of the i.MX6 DQ RM for more details.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Dec 2013 05:25:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277566#M31276</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-12-25T05:25:57Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q/D Muxed mode 16 bit NOR Flash interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277567#M31277</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I had a related question. Can I use the parallel flash to be the boot device in muxed mode as well? Since the freescale boards are using non-multiplexed I wanted to make sure that parallel nor flash can be used as a boot device in this this mode as well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Feb 2014 06:47:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277567#M31277</guid>
      <dc:creator>rajniks</dc:creator>
      <dc:date>2014-02-18T06:47:14Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6Q/D Muxed mode 16 bit NOR Flash interface</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277568#M31278</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Raj,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, you can. Please see section 8.5.1 of the MX6 reference manual. BOOT_CFG2[7:6] = 00 setting correspond to muxed 16-bit data boot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards.&lt;/P&gt;&lt;P&gt;Jorge.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Feb 2014 21:28:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6Q-D-Muxed-mode-16-bit-NOR-Flash-interface/m-p/277568#M31278</guid>
      <dc:creator>JorgeRama_rezRi</dc:creator>
      <dc:date>2014-02-18T21:28:16Z</dc:date>
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  </channel>
</rss>

