i.MX ProcessorsのトピックRe: imx50 ecspi ss_ctl control

imx50 ecspi ss_ctl control

michaelcarrier — Thu, 28 Feb 2013 00:11:47 GMT

I have an IMX50 EVK that I am trying to connect to a spi device. Our implementation requires the ss_ctl line to be active low during the entire 2 bytes transmit transaction. I have configured ecspi2 to be the master device and I am using the provided mxc_spi.c delivered with the MCIMX50EVK dev D board. I configured spidev2.0 to be my particular user space spi driver. I am attempting to send 2 bytes (0x5511) out the escpi2 device. Using an oscilloscope I can see the 2 data bytes and the associated clock. The slave select line goes low during the time each byte is transmitted. However, in between each byte the slave select line transitions high. I need this to remain low until the 2 bytes have been transmitted.

From what I am reading setting bit 8 in ECSPIx_CONFIGREG and configuring ECSPIx_PERIODREG to 0 should produce a slave select waveform such that the slave select line remains low during idle byte periods. What am I missing here?

Re: imx50 ecspi ss_ctl control

PeterChan — Wed, 20 Mar 2013 09:58:03 GMT

From i.MX50 reference manual 22.3.5.1.3, ECSPIx_CONFIGREG bit 8 should be clear (SS_CTL[0] is clear) for no SS negate between the SPI bursts. ECSPIx_CONREG:SMC must be 1 when using ECSPIx_CONFIGREG:SS_CTL to control the SS waveform.

Alternatively, you can set the ECSPIx_CONREG:BURST LENGTH=0x1F for 16 bit SPI burst and write 16-bit data to lower nibble of ECSPIx_TXDATA.

Re: imx50 ecspi ss_ctl control

YixingKong — Mon, 25 Mar 2013 03:56:43 GMT

Michael, if Peter's answer is good, please click Correct Answer.

Thanks,

Yixing