i.MX Processors中的主题 Re: DDR3 CLK connection

DDR3 CLK connection

tarterkit_ru — Wed, 05 Jun 2013 08:27:42 GMT

Hello, i want use 32bit bus DDR3.

In references with 64bits bus, used DRAM_SDCLK1 diff. signal.

In 32bit also may use DRAM_SDCLK1 or need use DRAM_SDCLK0?

Re: DDR3 CLK connection

weidong_sun — Wed, 05 Jun 2013 13:54:31 GMT

Hello,Pavel,

You can refer to DDR3 connections on i.MX53_Tablet_Design for your 32bit DDR3 bus. Please see attachment.

Regards,

Weidong

Re: DDR3 CLK connection

tarterkit_ru — Wed, 05 Jun 2013 14:05:54 GMT

Hello

I'm dont understand ... why imx53 schematic ...

schematic of imx53 not have questions, because bus is 32bits

imx6 have 64bits and i can't find references schematic with 32bit and datasheet don't have any instruction about CLK0/1 selection.

Re: DDR3 CLK connection

weidong_sun — Wed, 05 Jun 2013 14:42:17 GMT

Hello,Pavel,

I have ever confirmed the similar question with HW dept, it is no problem to use low 32bit bus of i.mx6 memory interface.

In i.MX SoC , The clock source of CLK0 & CLK1 is the same. So you can use them like this:

(1) Using same clock for reading or writing one 32 bit .

CS0: D0~D31 ( 2 DDR3 ICs)

CLK0

CS1: D0~D31 (2 DDR3 ICs)

CLK1
(2) Every 16bit uses same clock.

CS0: D0~D15 (1 DDR3 IC)

CLK0

CS0: D16~D31 (1 DDR3 IC)

CLK1

CS1: D0~D15 (1 DDR3 IC)

CLK0

CS1: D16~D31 (1 DDR3 IC)

CLK1

The above mothod is for you as a reference.

Regards,

Weidong

Re: DDR3 CLK connection

tarterkit_ru — Wed, 05 Jun 2013 14:50:33 GMT

Thanks!

Re: DDR3 CLK connection

tarterkit_ru — Wed, 05 Jun 2013 15:12:06 GMT

CS0: D0~D31 ( 2 DDR3 ICs)

CLK1

This variant is already possible?

Re: DDR3 CLK connection

weidong_sun — Wed, 05 Jun 2013 15:18:50 GMT

Hello,Pavel,

if you do like this, Is it convenient to control diffrential resistance of CLK1 during PCB design ?

In order to control resistance conveniently, I recommend 2nd solution:

(2) Every 16bit uses same clock.

CS0: D0~D15 (1 DDR3 IC)

CLK0

CS0: D16~D31 (1 DDR3 IC)

CLK1

CS1: D0~D15 (1 DDR3 IC)

CLK0

CS1: D16~D31 (1 DDR3 IC)

CLK1

Regards,

weidong

Re: DDR3 CLK connection

tarterkit_ru — Thu, 06 Jun 2013 05:10:07 GMT

Hello Sun,

It simply question, i get 3 reply without simply answer :smileyhappy:

I don't need recommendations and comments, please just tell me DRAM_CLK0 and DRAM_CLK1 it is fully equal or have specific with CS0/1

About recommendations, see pinout imx6, CLK0 and CLK1 is morror placed, as result - in references D0-D31 connected to CLK1 and D32-D63 connected to CLK0

Re: DDR3 CLK connection

Yuri — Thu, 06 Jun 2013 05:33:50 GMT

Pavel, good day !

really we can consider the DRAM_CLK0 and DRAM_CLK1 as the same clock.

But jitter should be taken into account, even when we use the same clock source,
split via buffers.

Re: DDR3 CLK connection

weidong_sun — Thu, 06 Jun 2013 05:36:21 GMT

Hello,Pavel,

Please refer to Yuri's advice for you ! I agree with him, too .

Regards,

Weidong