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    <title>topic Re: How do you disable caching and the interrupt controller on a i.MX6? in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274333#M30154</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Brian,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The basic cache maintenance code in U-Boot is here:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;A href="https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c" title="https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c"&gt;https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also see cache*.c in arch/arm/lib:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;A href="https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib" title="https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib"&gt;https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Feb 2014 00:46:12 GMT</pubDate>
    <dc:creator>EricNelson</dc:creator>
    <dc:date>2014-02-04T00:46:12Z</dc:date>
    <item>
      <title>How do you disable caching and the interrupt controller on a i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274330#M30151</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am having difficulties passing execution from on kernel to another.&amp;nbsp; I'm using Green Hills Integrity and their documentation states that i need to disable all cache and disable interrupt controller before i can run the newly loaded kernel. Unfortunately, I'm having a hard time finding any documentation on how to do this in the cortex A9.&amp;nbsp; Any body have any ideas on how to do this or where i can find some documentation?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Feb 2014 21:52:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274330#M30151</guid>
      <dc:creator>briannorman</dc:creator>
      <dc:date>2014-02-03T21:52:12Z</dc:date>
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    <item>
      <title>Re: How do you disable caching and the interrupt controller on a i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274331#M30152</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Brian,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you using U-Boot to load the image? If so, main-line U-Boot contains a command "dcache off" that you can use to disable the cache before launching Integrity.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Feb 2014 22:15:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274331#M30152</guid>
      <dc:creator>EricNelson</dc:creator>
      <dc:date>2014-02-03T22:15:29Z</dc:date>
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    <item>
      <title>Re: How do you disable caching and the interrupt controller on a i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274332#M30153</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes and no.&amp;nbsp; There is a lot of setup i haven't been able to figure out in Integrity yet so i initially boot with U-boot.&amp;nbsp; With U-boot i am able to bootm my kernels just fine. The problem that i have is i need a more intelligent boot program that can do more that u-boot so I'm trying to use an Integrity bootloader. I can load and start if from u-boot just fine.&amp;nbsp; Then, using the Integrity bootloader, i want to load and run my application.&amp;nbsp; According to the console output, my application is decompressing correctly and i get a message that the new kernel is booting, but then it hangs.&amp;nbsp; According to Green Hills documentation, i need to disable cache and interrupts before i jump to the new kernel, using a BSP function that i need to write.&amp;nbsp; I have wrote the function and i see that it is called, but i don't know how it is supposed to disable cache and interrupts.&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;Maybe i need to dive into u-boot code again and see what "dcache off" does.&amp;nbsp; Is there a U-boot command to disable the interrupt handler?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BTW, thanks for your response.&amp;nbsp; Any way you can help would be greatly appreciated, I've been beating my head against this for a couple weeks now.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Feb 2014 22:43:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274332#M30153</guid>
      <dc:creator>briannorman</dc:creator>
      <dc:date>2014-02-03T22:43:50Z</dc:date>
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    <item>
      <title>Re: How do you disable caching and the interrupt controller on a i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274333#M30154</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Brian,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The basic cache maintenance code in U-Boot is here:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;A href="https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c" title="https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c"&gt;https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also see cache*.c in arch/arm/lib:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;A href="https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib" title="https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib"&gt;https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Feb 2014 00:46:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-do-you-disable-caching-and-the-interrupt-controller-on-a-i/m-p/274333#M30154</guid>
      <dc:creator>EricNelson</dc:creator>
      <dc:date>2014-02-04T00:46:12Z</dc:date>
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