topic Re: Re: LVDS panel display corruption in i.MX Processors

LVDS panel display corruption

saurabh206 — Mon, 03 Mar 2014 08:31:32 GMT

Hi,

We are using custom hardware based on IMX6q.

LVDS panel is connected to hardware and some times we are getting display corruption.

How we can fixed this issue? What could be the reason behind this?

Thanks

Saurabh

Re: LVDS panel display corruption

saurabh206 — Mon, 10 Mar 2014 07:46:31 GMT

Hi,

Any Valuable guideline from Freescale Team?

Thanks

Saurabh

Re: LVDS panel display corruption

jamesbone — Tue, 11 Mar 2014 13:30:27 GMT

I would said that the issue it is timing related, you can review the fb structure that it is according to your LVDS display. I would recommend to measure the pixel clock to see it is according to the LVDS. Can you share your settings? Another way to review it is to slow down the resolution of the display to see if it is corrected.

Have a great day,
Jaime

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: LVDS panel display corruption

saurabh206 — Tue, 11 Mar 2014 18:36:52 GMT

Hi,

Thanks for taking interest and replay for this issue.

This issue occurs randomly. After reboot or suspend resume this issue disappear and visa verse.

I am using 1080p display Panel.

static struct fb_videomode ldb_modedb[] = {

"LDB-1080P60", 60, 1920, 1080, 6800,

128, 138 ,

22, 3,

80, 4,

FB_VMODE_NONINTERLACED,

FB_MODE_IS_DETAILED,},

};

And pll2_pfd_352M is used as clocking source for the LDB pixel clock,

Is It possible LDB pixel clock (pll2_pfd_352M ) has some jitter ?

Thanks

Saurabh

Re: LVDS panel display corruption

saurabh206 — Thu, 27 Mar 2014 17:33:33 GMT

Hi,

I have measured the clock signal

- LVDS0_CLK_P signal and it is always vary between 69.9 MHz to 73.3 MHz.

According to me it should be stable at any one value according to rounding clock rate. What could be wrong in this case?

In LDB split mode how the LVDS0_CLK_P and LVDS1_CLK_P generated from IPU_DI0_CLK?

When i have display corruption difference between LVDS0_CLK_P and LVDS1_CLK_P is approx 2 Hz, And for the proper picture this difference is between 0.2 Hz.

- Ideally this both clock LVDS0_CLK_P and LVDS1_CLK_P should be same because it is generated from same clock source.

Any Valuable comment from Freescale team?

Saurabh

Re: LVDS panel display corruption

karina_valencia — Thu, 27 Mar 2014 18:28:17 GMT

jamesbone can you continue with the follow up?

Re: LVDS panel display corruption

RodBorras — Thu, 27 Mar 2014 21:13:32 GMT

Saurabh,

Could you please check bit 17 of the IPUx_DI0_GENERAL register and make sure it is not the "Incorrect Setting" here below:

Regards,

Rod.

Re: LVDS panel display corruption

saurabh206 — Fri, 28 Mar 2014 11:25:19 GMT

Hi,

Rod

IPU_DI0_GENERAL --> 0x00300000;

IPU_DI0_BS_CLKGEN0 --> 0x00000010;

IPU_DI0_BS_CLKGEN1 --> 0x00010000;

Regards

Saurabh

Re: Re: LVDS panel display corruption

RodBorras — Fri, 28 Mar 2014 13:06:20 GMT

Hi Saurabh,

I have another customer with a similar problem. He is running Android, and it seems you are too.

The following patch seems to work for them. Would you please give it a try too?

Thanks,

Rod.

Re: LVDS panel display corruption

saurabh206 — Fri, 28 Mar 2014 15:43:10 GMT

Hi,

Rod

I have applied the patch and there a improvement.

I will test for longer period of time and provide you update.

Thanks

Saurabh

Re: LVDS panel display corruption

everlook — Thu, 17 Jul 2014 00:15:44 GMT

We are experiencing the same issue driving an LVDS panel. The patch (ENGR00304402) appears to be for the 3.0 kernel. Is there an updated patch the the 3.10.17 GA release?

Thanks,

Jeff

Re: LVDS panel display corruption

everlook — Thu, 17 Jul 2014 22:31:22 GMT

I was able to patch the 3.10.17 GA FSL kernel (using the code above) and the LVDS is now working without issue. We are still testing but all looks good. It appears I can not attach files to this post so I'm not sure how I can post the patch.

Thanks,

Jeff

Re: LVDS panel display corruption

boudewijn-ame — Fri, 24 Apr 2015 12:34:51 GMT

Hi Rod,

I have the same issue and i have solved it with your settings. Thank you. I would like to give some more information about what i saw. First i made a .bmp picture with only one pixel RGB colour = 127, 127 and 127. Then I send the whole picture to the screen using the following linux command:

dd if=/media/sda1/test.bmp bs=138 skip=1 > /dev/fb (The test image is a 1280x800 RGB565 bitmap file)

We then saw a shift in pixels:

When setting the following setting: addr 0x02640008 to 0x00020001 (was 0x00010000), the problem was fixed.

Below a measurement of the LVDS signals, CLK and RX1:

Red and blue are the incorrect image with shifted bits. Pink is the correct image.

Re: LVDS panel display corruption

RodBorras — Fri, 24 Apr 2015 15:39:20 GMT

Cool. Thanks for sharing!

Re: LVDS panel display corruption

yuefengzhu — Fri, 18 Mar 2016 03:17:39 GMT

Hello, Thank you for sharing you info, I got somehow similar problem. Could you guys kindly share with me how to set or read the register values for imx6? How do we check and change the value of the following registers?

IPU_DI0_GENERAL

IPU_DI0_BS_CLKGEN0

IPU_DI0_BS_CLKGEN1

Thank s a lot