topic Re: iMX6 NAND Address cycles definition in i.MX Processors

iMX6 NAND Address cycles definition

tarterkit_ru — Sat, 23 Feb 2013 09:36:42 GMT

Reference Manual have:

Table 8-11. NAND Boot eFUSE Descriptions: BOOT_CFG1[1:0] - Address Cycles

Fusemap Table 5-8. NAND Boot Fusemap: BOOT_CFG1[1:0] - Nand_Row_address_byte

What exactly need set to BOOT_CFG[1:0], all address cycles or only row address cycles?

Re: iMX6 NAND Address cycles definition

weidong_sun — Mon, 25 Feb 2013 06:43:35 GMT

It should be all address cycles.

Regards,

Weidong

Re: iMX6 NAND Address cycles definition

Rodrigue — Tue, 23 Jul 2013 11:54:25 GMT

Hi Weidong,

Are you sure? because the fuse map definition we use to have specifies the NAND row address bytes.

May you please confirm?

regards,

Re: iMX6 NAND Address cycles definition

Yuri — Wed, 24 Jul 2013 05:11:53 GMT

It looks like AddressCycles are Row Address Bytes, assuming Column Address Bytes = 2

Re: iMX6 NAND Address cycles definition

_timm — Wed, 07 Dec 2016 22:40:19 GMT

Hi: did we ever reach a definitive conclusion on this? I have the exact same situation: an OEM has set these fuses to 11b, but the NAND device that we are using has 2 column address bytes (fuses are 00b according to DQRM). So what is the correct answer?

Thanks,

Tim Meese

Re: iMX6 NAND Address cycles definition

Yuri — Thu, 08 Dec 2016 04:16:11 GMT

Hello,

The recent i.MX6 D/Q RM (IMX6DQRM, Rev. 3, 07/2015) clearly states in both tables,
that BOOT_CFG1[1:0] field defines Row Address Cycles.

Table 5-9 (NAND Boot Fusemap)

Table 8-10 (NAND Boot eFUSE Descriptions)

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf

Regards,

Yuri.