<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processorsのトピックddr benchmarking</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/ddr-benchmarking/m-p/266451#M27815</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;During another investigation I have noticed that the performance between SL and S are enormous when it comes to memory benchmarking. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;I have run the same code and used the same blocks within the ASIC so it should be identical result. The SL and S has the same ARM CPU (996MHz) and PL310 cache and DDR controller. The only difference are the L2$ size that are half in SL compared with S. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;My measurement shows that the difference are ~ 5 times better in S than in SL. Could you just elaborated with this result and also the expected benchmark for the DDR (400 MHz)?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 30 Jan 2014 10:12:29 GMT</pubDate>
    <dc:creator>mrlantz</dc:creator>
    <dc:date>2014-01-30T10:12:29Z</dc:date>
    <item>
      <title>ddr benchmarking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/ddr-benchmarking/m-p/266451#M27815</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;During another investigation I have noticed that the performance between SL and S are enormous when it comes to memory benchmarking. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;I have run the same code and used the same blocks within the ASIC so it should be identical result. The SL and S has the same ARM CPU (996MHz) and PL310 cache and DDR controller. The only difference are the L2$ size that are half in SL compared with S. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';"&gt;My measurement shows that the difference are ~ 5 times better in S than in SL. Could you just elaborated with this result and also the expected benchmark for the DDR (400 MHz)?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Jan 2014 10:12:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/ddr-benchmarking/m-p/266451#M27815</guid>
      <dc:creator>mrlantz</dc:creator>
      <dc:date>2014-01-30T10:12:29Z</dc:date>
    </item>
  </channel>
</rss>

