topic Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK in i.MX Processors

iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

tarterkit_ru — Wed, 20 Feb 2013 12:10:32 GMT

As see on shematic few iMX6 boards, RGMII PHY put to MAC 125MHz to ENET_REF_CLK/ENET_TX_CLKENET_TX_CLK pin.

What it for?

I can't see any describe of this in manuals and RGMII not require this signal.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

JorgeRama_rezRi — Wed, 20 Feb 2013 23:21:06 GMT

Hi Pavel,

There are 3 ways to supply the ENET clock. Please see chapter 11 of the attached, I think it will clarify.

Best regards.

Jorge.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

tarterkit_ru — Thu, 21 Feb 2013 14:11:12 GMT

Thanks, this document told about GPIO_16 refclock connections, but sabresd, sabresdlite boards use ENET_REF_CLK pin for reference clock and this document don't have any for it ...

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

fei_liu — Fri, 22 Feb 2013 09:09:55 GMT

GPIO_16 is for RMII reference clock;

ENET_REF_CLK is for RGMII reference clock.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

fei_liu — Wed, 22 May 2013 02:54:11 GMT

In RGMII Mode, only the pin "ENET_REF_CLK" could used as 125M reference clock input.

The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration).

In RMII Mode, only two pins "GPIO_16" and "RGMII_TX_CTL" could be used as the 50M reference clock. The clock source could be from external oscillator or internal PLL, need software configuration. Please refer the document "I.MX6 Hardware Development Guide", Chapter 11.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

MaxChou — Wed, 29 May 2013 05:58:33 GMT

Hi Fei Liu

We follow "I.MX6 Hardware Development Guide", Chapter 11,

and modify below pin for RMII interface

////////////////

MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,

MX6Q_PAD_ENET_MDIO__ENET_MDIO,

MX6Q_PAD_ENET_MDC__ENET_MDC,

MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,

MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,

MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,

MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,

MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,

MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,

MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT,

//////////////////

but we still have problem on RMII,

is anything else I should check in the kernel driver ??

How to config below pins ? Should I modify it to other function ??

///////////////////////////////////////////////////
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,

/////////////////////////////////////////////////////

Sincerely,Max

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

DuanFugang — Wed, 29 May 2013 07:39:36 GMT

Kernel driver don’t support RMII, but we have patch for this. （You can email to me to get it： b38611@freescale.com）

Don’t care about RGMII pad control.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

MaxChou — Mon, 03 Jun 2013 01:57:56 GMT

Hi Fugang Duan

it is sloved, thanks!!

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

lukascaha — Wed, 29 Jan 2014 10:04:15 GMT

hello,

we have similar problem with custom board with MX6S/DL. PHY is LAN8720 and i u-boot works ok.

In kernel, iomux and clock generated by gpio_16 is ok.

I don't understand - kernel driver don't support RMII, but on MX6SL dev board (and processor) is only RMII.

I know this is allmost another processor, but changes in u-boot are inpired by mx6slevk.c

Ist about RMII support for MX6S/DL/Q ?

For what kernel branch is patch applicable - is RMII support better in some branches - I use imx_3.0.35_1.1.0

thank

Lukas

Re: Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

DuanFugang — Fri, 25 Apr 2014 09:07:27 GMT

Attached the patch for RMII base on kernel 3.0.35.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

mchaplet — Tue, 26 Aug 2014 10:02:17 GMT

Thanks for this patch !

I also use LAN8720 and RMII connection to it from a IMX6S and it works well in U-Boot but last kernel 3.10.17 from imx git seems to disable 50MHz PLL.

How to force it in DTS ?

I've yet tried to replace clks190 - "ptp" by "enet_ref" in fec controller description (imx6qdl.dtsi) without success.

Thanks,

Martin

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

shabeerbadarudh — Fri, 24 Oct 2014 05:55:56 GMT

Hi Martin,

We are also facing the same issue. Did you have any luck in 3.10.17?

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

marcocavallini — Fri, 10 Apr 2015 10:41:10 GMT

Hi,

is it working your i.MX6S kernel 3.10.17 with LAN8720 and RMII connection?

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

marcocavallini — Fri, 10 Jul 2015 15:16:07 GMT

Here it is at last ;-)

Cordiali Saluti / Kindest Regards / Mit freundlichen Grüßen

Marco Cavallini | KOAN sas | Bergamo - Italia

embedded and real-time software engineering

Phone:+39-035-255.235 - Fax:+39-178-22.39.748

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

shabeerbadarudh — Thu, 12 Nov 2015 15:13:19 GMT

sorry for the late reply.

Yes, it was worked in our platform. (i.MX6S kernel 3.10.17 with LAN8720 and RMII)

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

yinchunhui — Mon, 11 Apr 2016 05:59:30 GMT

hello Fei Liu

You said "The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration)."

I want to ask how to routed from GPIO_16?What is the detail configuration?

Now I can generate the 125M clock at the GPIO_16.

Thank you very much

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

fei_liu — Mon, 11 Apr 2016 07:55:50 GMT

ENET_REF_CLK is the input pin for RGMII reference clock, so if you want to use GPIO_16 to provide the 125M clock, you should connect GPIO_16 to ENENT_REF_CLK, and be careful, the voltage level might be different, you might need an level shift.

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

yinchunhui — Mon, 11 Apr 2016 08:00:33 GMT

thank you very much!

But I see you say"need software configuration",is there any method though software?

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

fei_liu — Mon, 11 Apr 2016 08:07:29 GMT

The software configuration is just for outputting 125M on GPIO_16, since you have already done, no additional operations or configurations are needed.

Best regards,

Frank Liu

Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

yinchunhui — Mon, 11 Apr 2016 08:11:21 GMT

ok,I know,thank you very much!