<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Peer-to-Peer using two iMX6Q End-Point SoC in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264895#M27376</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are working on your issue,&amp;nbsp; as soon as we get some information we get back to you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 29 Jan 2014 18:36:49 GMT</pubDate>
    <dc:creator>jamesbone</dc:creator>
    <dc:date>2014-01-29T18:36:49Z</dc:date>
    <item>
      <title>Peer-to-Peer using two iMX6Q End-Point SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264894#M27375</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Hello,&lt;BR /&gt; &lt;BR /&gt; We are designing a PCIe based system in which iMX6Q might be used in End-Point mode. I went through couple of Freescale links (shown below) and realized many people are trying to achieve the same.&lt;BR /&gt; &lt;BR /&gt; &lt;A href="https://owa.crystalvision.tv/owa/redir.aspx?C=nfIOk4wTsESWBMsh5QV5WYiIWmeZ8NAI2xmq5zOmb_7pdxe0GsawyJKfEZWLKH1PTSTlyLF5YMc.&amp;amp;URL=https%3a%2f%2fcommunity.freescale.com%2fdocs%2fDOC-95014" target="_blank"&gt;https://community.freescale.com/docs/DOC-95014&lt;/A&gt;&lt;BR /&gt; &lt;A href="https://owa.crystalvision.tv/owa/redir.aspx?C=nfIOk4wTsESWBMsh5QV5WYiIWmeZ8NAI2xmq5zOmb_7pdxe0GsawyJKfEZWLKH1PTSTlyLF5YMc.&amp;amp;URL=https%3a%2f%2fcommunity.freescale.com%2fthread%2f316790" target="_blank"&gt;https://community.freescale.com/thread/316790&lt;/A&gt;&lt;BR /&gt; &lt;BR /&gt; we are trying to achieve Peer-to-Peer communication using 2 iMX6Q in End-Point mode. There were few questions which were going on in my mind and your expertise would be of immense help:&lt;BR /&gt; &lt;BR /&gt; 1. If two iMX6Q are configured in End-Point mode and are connected to the Host processor through some PCI Express switch. Is it possible to generate interrupt (Message Signalled Interrupt or MSIs) from&lt;BR /&gt;&amp;nbsp; one End-Point to another? What configuration is required to do so?&lt;BR /&gt; &lt;BR /&gt; 2. I came to know about iATU (Address Translation Unit), I read about it from Processor guide and the code in arch/.../pcie.c (I guess written by you :)). it looks outbound initialization code use&lt;SPAN&gt;s&lt;/SPAN&gt; hard coded&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; physical address 0x40000000 as the target address (I guess upper 256MB of 1 GB RAM are being used for the test purposes) of the mapping. &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; In the real scenario like ours i.e. Peer-to-Peer where we are not aware of the physical address of the target device in prior, as End-Point devices may come and go at any time&lt;SPAN&gt;,&lt;/SPAN&gt; How should I setup the&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; base address to target address mapping?&lt;BR /&gt; &lt;BR /&gt; regards&lt;BR /&gt; Salil&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Jan 2014 15:52:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264894#M27375</guid>
      <dc:creator>salil</dc:creator>
      <dc:date>2014-01-29T15:52:29Z</dc:date>
    </item>
    <item>
      <title>Re: Peer-to-Peer using two iMX6Q End-Point SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264895#M27376</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are working on your issue,&amp;nbsp; as soon as we get some information we get back to you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Jan 2014 18:36:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264895#M27376</guid>
      <dc:creator>jamesbone</dc:creator>
      <dc:date>2014-01-29T18:36:49Z</dc:date>
    </item>
    <item>
      <title>Re: Peer-to-Peer using two iMX6Q End-Point SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264896#M27377</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks! James, that would be really helpful.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Jan 2014 07:37:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264896#M27377</guid>
      <dc:creator>salil</dc:creator>
      <dc:date>2014-01-30T07:37:48Z</dc:date>
    </item>
    <item>
      <title>Re: Peer-to-Peer using two iMX6Q End-Point SoC</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264897#M27378</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="background: white;"&gt;&lt;SPAN style="font-family: 'Calibri','sans-serif'; font-size: 11pt;"&gt;I cannot access the link&lt;/SPAN&gt; &lt;SPAN lang="EN" style="font-family: 'Helvetica','sans-serif'; color: #3d3d3d; font-size: 10pt;"&gt;&lt;A href="https://owa.crystalvision.tv/owa/redir.aspx?C=nfIOk4wTsESWBMsh5QV5WYiIWmeZ8NAI2xmq5zOmb_7pdxe0GsawyJKfEZWLKH1PTSTlyLF5YMc.&amp;amp;URL=https%3a%2f%2fcommunity.freescale.com%2fthread%2f316790"&gt;https://community.freescale.com/thread/316790&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Calibri','sans-serif'; font-size: 11pt;"&gt;In theory, &lt;/SPAN&gt;you can use your special target address instead of&amp;nbsp; the hardcode(0x40000000), the iATU will help on the translation between base address and target address.&lt;/P&gt;&lt;P&gt;And the address should be 64k aligned, it is the minimum translation unit, I remembered.&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Feb 2014 01:57:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Peer-to-Peer-using-two-iMX6Q-End-Point-SoC/m-p/264897#M27378</guid>
      <dc:creator>b47504</dc:creator>
      <dc:date>2014-02-10T01:57:02Z</dc:date>
    </item>
  </channel>
</rss>

