topic I.Mx SDRAM interfacing in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/I-Mx-SDRAM-interfacing/m-p/158216#M2718 <HTML><HEAD></HEAD><BODY><P>In the MX53SUG.pdf the explanation for DDR_INPUT field in the IOMUX chapter is this,</P><P>"DDR_INPUT (1 bit ddr_input control)—Needed when interfacing DDR memories."</P><P></P><P>But nowhere it is mentioned whether or not to enable this bit? And to which pins this should be enabled?</P><P>Any ideas on what is the CMOS input mode and Differential input mode?</P><P></P><P><BR /><BR /></P></BODY></HTML> Wed, 02 May 2012 06:40:52 GMT positron 2012-05-02T06:40:52Z I.Mx SDRAM interfacing https://community.nxp.com/t5/i-MX-Processors/I-Mx-SDRAM-interfacing/m-p/158216#M2718 <HTML><HEAD></HEAD><BODY><P>In the MX53SUG.pdf the explanation for DDR_INPUT field in the IOMUX chapter is this,</P><P>"DDR_INPUT (1 bit ddr_input control)—Needed when interfacing DDR memories."</P><P></P><P>But nowhere it is mentioned whether or not to enable this bit? And to which pins this should be enabled?</P><P>Any ideas on what is the CMOS input mode and Differential input mode?</P><P></P><P><BR /><BR /></P></BODY></HTML> Wed, 02 May 2012 06:40:52 GMT https://community.nxp.com/t5/i-MX-Processors/I-Mx-SDRAM-interfacing/m-p/158216#M2718 positron 2012-05-02T06:40:52Z