topic Re: DDR layout question in i.MX Processors

DDR layout question

yar — Mon, 16 Dec 2013 14:28:57 GMT

Hello,

I make layout for custom design i.mx28 board. At the moment I'm trying to understand DDR layout rule.

In this document - http://www.freescale.com/files/32bit/doc/app_note/AN4215.pdf on page 9, describes rules are quite blurry.

So I found this document http://www.freescale.com/files/dsp/doc/app_note/AN3963.pdf page 9 describes all very clear but rules conflict with AN4215 document.

For example:

AN4215: Address and Command signals - length matched to each other within 200 mils

AN3963: Address and Bank - ≤ Clock length, Match the signals ± 20 mils

AN4215: Data signals - Lengths must be matched within 100 mils of the corresponding data strobes

AN3963: Data and Buffer - ≤ Clock length and Match the signals ± 20 mils or Max byte Group 1 length ≤ Clock length

What rules should be trusted?

Thanks.

Re: DDR layout question

peteewg — Mon, 16 Dec 2013 15:04:51 GMT

If you're concerned about it, go with the tightest specification.

In general though, for a ~600MHz interface you should be okay as long as you match all the traces to about 1cm and pairs (e.g. clks + strobes) to 2mm.

Make sure you have a good ground plane underneath the signals and you'll be fine. Also if it makes it easier you can swap around the data-pins (but you can't do that with address pins).

Re: DDR layout question

yar — Mon, 16 Dec 2013 15:57:35 GMT

Hello Peter thanks for answer.

Well if I do this:

Match this traces to about 1cm:

EMI_A[0-14]

EMI_D[00-15]

EMI_BA0, EMI_BA1, EMI_BA2

EMI_CASN, EMI_CE0N, EMI_CKE, EMI_ODT0, EMI_RASN, EMI_WEN

EMI_DQM0, EMI_DQM1

Match this traces to 2mm:

EMI_DQS0_N

EMI_DQS0_P

EMI_DQS1_N

EMI_DQS1_P

EMI_CLK_N

EMI_CLK_P

Under such conditions, all should be okay?

Re: DDR layout question

EgleTeam — Mon, 16 Dec 2013 16:17:28 GMT

Yar, match:

* Diff pairs (N & P net) the shorter the better (<0.5mm).

* Data lanes (for example: DQ0-DQ7, DQS0, DQM0) less than 2.5mm.

* ADDRESS and COMMAND are not so important: less than 10mm, like Peter says, should be enough.

* Clock DP should be longer than the rest of nets (at least data, clock and strobes).

* Place, if possible, the same number of vias and route in the same layers: data, clock and strobes.

Max frequency is about 200Mhz so matching length is not critical but good ground planes and "power delivery network": "robust" power plane for supply, 0.5-1 bypass capacitors for each VDD ball, 1 bulk capacitor each 10 VDD balls, and so on.

Re: DDR layout question

peteewg — Mon, 16 Dec 2013 16:19:27 GMT

That sounds fine to me, it's a bit more relaxed than the official guidelines, but you shouldn't run into any problems, obviously the closer you can match trace lengths the better.

Just for clarity, All traces to min-length to max-length < 1cm

AND

EMI_DQS0_N = EMI_DQS0_P +/- 2mm

EMI_DQS1_N = EMI_DQS1_P +/- 2mm

EMI_CLK_N = EMI_CLK_P +/- 2mm

There are a couple of layout examples in AN4215 and the actual layout of the EVK are here:

https://www.freescale.com/webapp/Download?colCode=IMX28_EVK_DESIGN_FILES_R10&appType=license&location=null&fr=gtl&Parent…

If your layout/schematic tool supports it, you could just import the layout the apps guys have already done, or copy it manually. The only reason not to do that is if you need a shorter distance between the devices (it's about 12mm in the EVK layout).

Otherwise you can use the breakouts in section 5.5 of AN4215. And adjust the parallel lines to meet your board constraints (check with your assembly house on the minimum distance between BGAs)