topic CSI Parallel Interface on i.MX6 Dualite in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/CSI-Parallel-Interface-on-i-MX6-Dualite/m-p/263605#M26994 <HTML><HEAD></HEAD><BODY><P>Hi</P><P>I am using i.MX6 Duallite processor to interface a camera Sensor via its CSI-Parallel Port.</P><P>The Camera Sensor requires a Master CLK ( a free running clock) which need to be supplied from the processor.</P><P>In turn the Camera output consists of Data Lines [0:9], HSYNC, VSYNC and Pixel clock.</P><P>Now the CSI Interface Pin-outs on the i.MX6 Dual Lite shows that the CSI0_MCLK is muxed with CSI0_HSYNC. In this case, what is the suggestion by Freescale community regarding the connectivity of MCLK and HSYNC signals?</P></BODY></HTML> Thu, 03 Oct 2013 21:13:46 GMT krishnaprasada 2013-10-03T21:13:46Z CSI Parallel Interface on i.MX6 Dualite https://community.nxp.com/t5/i-MX-Processors/CSI-Parallel-Interface-on-i-MX6-Dualite/m-p/263605#M26994 <HTML><HEAD></HEAD><BODY><P>Hi</P><P>I am using i.MX6 Duallite processor to interface a camera Sensor via its CSI-Parallel Port.</P><P>The Camera Sensor requires a Master CLK ( a free running clock) which need to be supplied from the processor.</P><P>In turn the Camera output consists of Data Lines [0:9], HSYNC, VSYNC and Pixel clock.</P><P>Now the CSI Interface Pin-outs on the i.MX6 Dual Lite shows that the CSI0_MCLK is muxed with CSI0_HSYNC. In this case, what is the suggestion by Freescale community regarding the connectivity of MCLK and HSYNC signals?</P></BODY></HTML> Thu, 03 Oct 2013 21:13:46 GMT https://community.nxp.com/t5/i-MX-Processors/CSI-Parallel-Interface-on-i-MX6-Dualite/m-p/263605#M26994 krishnaprasada 2013-10-03T21:13:46Z Re: CSI Parallel Interface on i.MX6 Dualite https://community.nxp.com/t5/i-MX-Processors/CSI-Parallel-Interface-on-i-MX6-Dualite/m-p/263606#M26995 <HTML><HEAD></HEAD><BODY><P>Please reference to the SARBE SD board, the pin named CSI0_MCLK is configure as HSYNC input and the Master clock for camera is connected to the pin named GPIO_0. The GPIO_0 can provide clock output function. </P></BODY></HTML> Fri, 04 Oct 2013 05:46:33 GMT https://community.nxp.com/t5/i-MX-Processors/CSI-Parallel-Interface-on-i-MX6-Dualite/m-p/263606#M26995 aven_tsao 2013-10-04T05:46:33Z