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    <title>i.MX ProcessorsのトピックRe: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260014#M25782</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I observed the value of srx_dis by flexcan driver (in the path &lt;SPAN class="st"&gt;/&lt;EM&gt;sys/devices/platform/FlexCAN&lt;/EM&gt;.0/&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;and the value 1 before and after the driver up.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 13 May 2013 05:39:04 GMT</pubDate>
    <dc:creator>Ushnek</dc:creator>
    <dc:date>2013-05-13T05:39:04Z</dc:date>
    <item>
      <title>Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260010#M25778</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I am trying to setup the CAN bus for transmitting and receiving message by socketcan library. (cansend and candump)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; However, the flexcan(can0) always can receive the message frame which send by itself even if I set the register "SRX_DIS" of flexcan to "1".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Would someone help me to set this up please?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 10 Apr 2013 08:06:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260010#M25778</guid>
      <dc:creator>Ushnek</dc:creator>
      <dc:date>2013-04-10T08:06:17Z</dc:date>
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    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260011#M25779</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Which BSP are you using?&amp;nbsp; and apply all the patches?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For your information, here is the link of BSP and patches for i.MX53.&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX53_SW"&gt;http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX53_SW&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 12 Apr 2013 03:30:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260011#M25779</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2013-04-12T03:30:30Z</dc:date>
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    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260012#M25780</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jimmy,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I use the QSB BSP and modify its config for CAN bus transciveing based on mx53_loco and mx53_ard.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; The CAN port could send and receive message with another CAN device. (by cantest tool)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; However, it receive the message sent by itself, too. This is not normal behavior in CAN spec.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I have added all of the patches for iMX53 when I built image, especially patch about CAN bus.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Thank you and your response.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 17 Apr 2013 05:54:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260012#M25780</guid>
      <dc:creator>Ushnek</dc:creator>
      <dc:date>2013-04-17T05:54:28Z</dc:date>
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    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260013#M25781</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;Can you please explain how/when are you setting the srx_dis is being set?&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;Can you try read with memtool the FLEXCANx_MCR register? check if the SRX_DIS bit is really being set or not.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;I am wondering if the feature is really implemented.(if the driver ever sets the bit)&lt;/P&gt;&lt;P style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;Or if the bit is set during initialization. (It must be set during init, otherwise it may fail)&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 May 2013 13:46:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260013#M25781</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-05-09T13:46:48Z</dc:date>
    </item>
    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260014#M25782</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I observed the value of srx_dis by flexcan driver (in the path &lt;SPAN class="st"&gt;/&lt;EM&gt;sys/devices/platform/FlexCAN&lt;/EM&gt;.0/&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;and the value 1 before and after the driver up.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2013 05:39:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260014#M25782</guid>
      <dc:creator>Ushnek</dc:creator>
      <dc:date>2013-05-13T05:39:04Z</dc:date>
    </item>
    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260015#M25783</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Did you try using &lt;SPAN style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;/unit_tests/memtool?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;if you are accessing driver &lt;SPAN style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;/&lt;/SPAN&gt;&lt;EM style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;sys/devices/platform/FlexCAN&lt;/EM&gt;&lt;SPAN style="font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; background-color: #ffffff;"&gt;.0/&lt;/SPAN&gt; I am not sure you are seeing the real srx_dis... but simply a mirrored value or variable of the driver.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With the memtool you will see the exact value on the CAN peripheral register. From ref manual addresses are &lt;/P&gt;&lt;P&gt;FLEXCAN-1_MCR is 53FC_8000h base + 0h offset = 53FC_8000h&lt;/P&gt;&lt;P&gt;FLEXCAN-2_MCR is 53FC_C000h base + 0h offset = 53FC_C000h&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please then check the actual register value and let me know.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 May 2013 23:35:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260015#M25783</guid>
      <dc:creator>ioseph_martinez</dc:creator>
      <dc:date>2013-05-13T23:35:43Z</dc:date>
    </item>
    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260016#M25784</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ushnek, please click Correct Answer/Helpful Answer if Ioseph Martinez answered your questions.&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yixing&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 May 2013 03:20:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260016#M25784</guid>
      <dc:creator>YixingKong</dc:creator>
      <dc:date>2013-05-21T03:20:29Z</dc:date>
    </item>
    <item>
      <title>Re: Is iMX53 FlexCAN SRX_DIS bit setting fail?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260017#M25785</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I had used memtool to read register but it would print below message.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Reading 0x1 count starting at adUnhandled fault: external abort on non-linefetch (0x1018) at 0x2aac5000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; dress 0x53FC8000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Bus error&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; So I am not sure these address could be read by memtool. Maybe these address are not in the trustzone with MMU?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; By the way, I find the solution for my flexcan driver issue. According the documentation of socketcan "can.txt"&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; point this description in section 3.2 and 6.2, I add the device flag "IFF_ECHO" in flexcan/drv.c. The echo message&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; would not be received itself and srx_dis register could be workable, too. I don't know why flexcan source code is&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; not add this flag in default.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; After all, the srx_dis bit is workable in my board but the flexcan driver need add IFF_ECHO flag to stop receiving&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; message sent itself.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;Ushnek&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 May 2013 06:01:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Is-iMX53-FlexCAN-SRX-DIS-bit-setting-fail/m-p/260017#M25785</guid>
      <dc:creator>Ushnek</dc:creator>
      <dc:date>2013-05-21T06:01:39Z</dc:date>
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