topic Re: IOMUX/DCD DRAM configuration confusion... in i.MX Processors

IOMUX/DCD DRAM configuration confusion...

EdSutter — Tue, 05 Nov 2013 15:05:17 GMT

I'm using a SABRESDB which has 64-bit DDR3 DRAM. My custom hardware will have 32-bit DDR3 DRAM.

So, I'm working through creation of my custom DCD setup (in latest uboot, this is the file board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg).

I started with the very helpful spreadsheet from https://community.freescale.com/docs/DOC-93963, and I'm now just walking through this

to make sure I understand the settings.

I see at least one case where the DDR_SEL field is set as RESERVED when it appears to me that it should be set to DDR3.

I realize that in many cases, the PAD setting is taken from the corresponding GRP register, but according to the reference manual

this DDR_SEL field of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET is not covered by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.

The line (taken from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg):

DATA 4 0x020e057c 0x00020030

is for the IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, and leaves the DDR_SEL bitfield set to 00 (RESERVED0).

I cross-checked this with the older (LTIB) uboot which has the code in flash_header.S and it has this line:

MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)

which not only doesn't set the DDR_SEL bits, but also has a different value for the DDR_INPUT field.

The spreadsheet tool appears to match the setting that was used in flash_header.S.

Since the DRAM_RESET pin is not covered by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE setting, shouldn't its DDR_SEL bitfield be 11 (DDR3)?

Also, it seems to me that the DDR_INPUT should be 0 (CMOS)???

I've ran with both of these configurations and the system seems to work just fine; but I'd like to make sure I'm properly configuring these pins.

Can someone clarify what settings are the correct ones here?

Re: IOMUX/DCD DRAM configuration confusion...

JorgeRama_rezRi — Thu, 21 Nov 2013 21:41:15 GMT

Hi Ed,

Yes, for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET[DDR_SEL] you should use 00. Long story short, it affects other pins in the processor and 00 is the correct setting. You can use it since it doesn't affect the DDR speed. Our reference manual should be updated with this info soon. 00 will be the value to select and the rest will be reserved.

And about the DDR_INPUT bit, it should be 0 1. You may notice later that we have this same setting on the DDR clock pins configurations (I've received this question before too), we also set them as CMOS instead of differential. This is why: Configuring DDR clock pins as CMOS inputs / Differential inputs is meaningless, because the DDR clock pins are never inputs. They are only outputs. What is CMOS input / Differential input? This configures the voltage level at which the pins senses a transition from logic low to logic high and from logic high to logic low. In differential mode, the pins transitions from logic low to logic high at 50% logic level going from low level to high level (for DDR3, 0.75V). The pin transitions from logic high to logic low at 50% logic level going from high level to low level. In CMOS input mode, the pins transitions from logic low to logic high at 80% logic level going from low level to high level (for DDR3, 1.2V). The pin transitions from logic high to logic low at 20% logic level going from high level to low level (for DDR3, 0.3V). While this is not technically part of the DDR standards, the pin design group decided to add this feature (CMOS mode) in case there were timing problems. Since differential mode works as expected, it is the preferred mode. If it would never used for DDR clock pins, why is it included? All DDR3 pads/pins are designed together as a group. They are identical, and have identical functionality.

Best regards.

Jorge.

Re: Re: IOMUX/DCD DRAM configuration confusion...

EdSutter — Mon, 25 Nov 2013 20:50:07 GMT

Jorge,

Ok, thanks for responding. I wanna be clear on this...

You're saying that the setting in LTIB u-boot...

MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)

is correct and the value in newer mainline uboot (which uses a totally different mechanism to build the DCD)...

DATA 4 0x020e057c 0x00020030

is incorrect, right? I wanna make sure I get this right because empirically both settings work,

and having this wrong could possibly cause long-term degradation of the device.

Thanks,

Re: IOMUX/DCD DRAM configuration confusion...

JorgeRama_rezRi — Tue, 03 Dec 2013 21:52:37 GMT

Hi Ed,

Actually the preferred value for register 0x020e057c is 0x00020030. This will set the input as differential. And yes, both values work fine, so the other setting is not exactly wrong, but just not preferred because of the threshold values.

Best regards.

Jorge.

Re: IOMUX/DCD DRAM configuration confusion...

EdSutter — Wed, 04 Dec 2013 13:11:11 GMT

Jorge,

Ok, so if 0x00020030 is the correct setting for register 0x020e057c, this equates to DDR_INPUT bit being '1' (Differential).

It would probably be a good idea to remove the bottom paragraph of your earlier post that says it should be '0', just to avoid confusion for future readers.

Thanks!

Re: IOMUX/DCD DRAM configuration confusion...

takashitakahash — Fri, 06 Jun 2014 02:14:24 GMT

Hi Jorge

About the IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.

In the below attached example set to the Bit#19.18 [DDR_SEL] = 00;

But I think I select the DDR3 = "11" is correct.

Debated on this Comunity "00" is the correct answer?

Also in the same register Bit # 17 [DDR_INPUT] is 0 in the example configuration,

but in the Community Bit # 17="1" ,Is this correct?

-------------------- Example settings-------------------------------------------

/=============================================================================

//init script for i.MX6DL DDR3

//=============================================================================

// Revision History

// v01

//=============================================================================

wait = on

//=============================================================================

// Disable WDOG

//=============================================================================

//setmem /16 0x020bc000 = 0x30

//=============================================================================

// Enable all clocks (they are disabled by ROM code)

//=============================================================================

setmem /32 0x020c4068 = 0xffffffff

setmem /32 0x020c406c = 0xffffffff

setmem /32 0x020c4070 = 0xffffffff

setmem /32 0x020c4074 = 0xffffffff

setmem /32 0x020c4078 = 0xffffffff

setmem /32 0x020c407c = 0xffffffff

setmem /32 0x020c4080 = 0xffffffff

setmem /32 0x020c4084 = 0xffffffff

//=============================================================================

// IOMUX

//=============================================================================

//DDR IO TYPE:

setmem /32 0x020e0774 = 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

setmem /32 0x020e0754 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE

//CLOCK:

setmem /32 0x020e04ac = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

setmem /32 0x020e04b0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

//ADDRESS:

setmem /32 0x020e0464 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

setmem /32 0x020e0490 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

setmem /32 0x020e074c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS

//CONTROL:

setmem /32 0x020e0494 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

setmem /32 0x020e04a0 = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

setmem /32 0x020e04b4 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

setmem /32 0x020e04b8 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

setmem /32 0x020e076c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS

//DATA STROBE:

setmem /32 0x020e0750 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

setmem /32 0x020e04bc = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

setmem /32 0x020e04c0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

setmem /32 0x020e04c4 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

setmem /32 0x020e04c8 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

setmem /32 0x020e04cc = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4

setmem /32 0x020e04d0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5

setmem /32 0x020e04d4 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6

setmem /32 0x020e04d8 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7

//DATA:

setmem /32 0x020e0760 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE

setmem /32 0x020e0764 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS

setmem /32 0x020e0770 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS

setmem /32 0x020e0778 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS

setmem /32 0x020e077c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS

setmem /32 0x020e0780 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS

setmem /32 0x020e0784 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS

setmem /32 0x020e078c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS

setmem /32 0x020e0748 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS

setmem /32 0x020e0470 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

setmem /32 0x020e0474 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

setmem /32 0x020e0478 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

setmem /32 0x020e047c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

setmem /32 0x020e0480 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4

setmem /32 0x020e0484 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5

setmem /32 0x020e0488 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6

setmem /32 0x020e048c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7

//=============================================================================

// DDR Controller Registers

//=============================================================================

// Manufacturer: Micron

// Device Part Number: MT41J128M16HA-15E

// Clock Freq.: 400MHz

// Density per CS in Gb: 8

// Chip Selects used: 1

// Number of Banks: 8

// Row address: 14

// Column address: 10

// Data bus width 64

//=============================================================================

setmem /32 0x021b0800 = 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

// write leveling, based on Freescale board layout and T topology

// For target board, may need to run write leveling calibration

// to fine tune these settings

// If target board does not use T topology, then these registers

// should either be cleared or write leveling calibration can be run

setmem /32 0x021b080c = 0x001F001F

setmem /32 0x021b0810 = 0x001F001F

setmem /32 0x021b480c = 0x001F001F

setmem /32 0x021b4810 = 0x001F001F

//######################################################

//calibration values based on calibration compare of 0x00ffff00:

//Note, these calibration values are based on Freescale's board

//May need to run calibration on target board to fine tune these

//######################################################

//Read DQS Gating calibration

setmem /32 0x021b083c = 0x4220021F // MPDGCTRL0 PHY0

setmem /32 0x021b0840 = 0x0207017E // MPDGCTRL1 PHY0

setmem /32 0x021b483c = 0x4201020C // MPDGCTRL0 PHY1

setmem /32 0x021b4840 = 0x01660172 // MPDGCTRL1 PHY1

//Read calibration

setmem /32 0x021b0848 = 0x4A4D4E4D // MPRDDLCTL PHY0

setmem /32 0x021b4848 = 0x4A4F5049 // MPRDDLCTL PHY1

//Write calibration

setmem /32 0x021b0850 = 0x3F3C3D31 // MPWRDLCTL PHY0

setmem /32 0x021b4850 = 0x3238372B // MPWRDLCTL PHY1

//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):

setmem /32 0x021b081c = 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3

setmem /32 0x021b0820 = 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3

setmem /32 0x021b0824 = 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3

setmem /32 0x021b0828 = 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3

setmem /32 0x021b481c = 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3

setmem /32 0x021b4820 = 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3

setmem /32 0x021b4824 = 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3

setmem /32 0x021b4828 = 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3

//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented

//setmem /32 0x021b08c0 = 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

//setmem /32 0x021b48c0 = 0x24911492

// Complete calibration by forced measurement:

setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr

setmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr

//MMDC init:

setmem /32 0x021b0004 = 0x0002002D // MMDC0_MDPDC

setmem /32 0x021b0008 = 0x00333030 // MMDC0_MDOTC

setmem /32 0x021b000c = 0x3F435313 // MMDC0_MDCFG0

setmem /32 0x021b0010 = 0xB66E8B63 // MMDC0_MDCFG1

setmem /32 0x021b0014 = 0x01FF00DB // MMDC0_MDCFG2

setmem /32 0x021b0018 = 0x00001740 // MMDC0_MDMISC

//NOTE about MDMISC RALAT:

//MDMISC: RALAT kept to the high level of 5 to ensure stable operation at 528MHz.

//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:

//a. better operation at low frequency

//b. Small performence improvment

setmem /32 0x021b001c = 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up

setmem /32 0x021b002c = 0x000026d2 // MMDC0_MDRWD; recommend to maintain the default values

setmem /32 0x021b0030 = 0x00431023 // MMDC0_MDOR

setmem /32 0x021b0040 = 0x00000027 // CS0_END

setmem /32 0x021b0000 = 0x831A0000 // MMDC0_MDCTL

// Mode register writes

setmem /32 0x021b001c = 0x04008032 // MMDC0_MDSCR, MR2 write, CS0

setmem /32 0x021b001c = 0x00008033 // MMDC0_MDSCR, MR3 write, CS0

setmem /32 0x021b001c = 0x00048031 // MMDC0_MDSCR, MR1 write, CS0

setmem /32 0x021b001c = 0x05208030 // MMDC0_MDSCR, MR0 write, CS0

setmem /32 0x021b001c = 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0

//setmem /32 0x021b001c = 0x0400803A // MMDC0_MDSCR, MR2 write, CS1

//setmem /32 0x021b001c = 0x0000803B // MMDC0_MDSCR, MR3 write, CS1

//setmem /32 0x021b001c = 0x00048039 // MMDC0_MDSCR, MR1 write, CS1

//setmem /32 0x021b001c = 0x05208038 // MMDC0_MDSCR, MR0 write, CS1

//setmem /32 0x021b001c = 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1

setmem /32 0x021b0020 = 0x00005800 // MMDC0_MDREF

setmem /32 0x021b0818 = 0x00011117 // DDR_PHY_P0_MPODTCTRL

setmem /32 0x021b4818 = 0x00011117 // DDR_PHY_P1_MPODTCTRL

setmem /32 0x021b0004 = 0x0002556D // MMDC0_MDPDC with PWDT bits set

setmem /32 0x021b0404 = 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

setmem /32 0x021b001c = 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

------------------------------------------------

Thnak you,

Best Regards.

T.Takahashi