<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: PCIe pins direction</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258465#M25253</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The added resistors didn't help.&amp;nbsp; Thanks for your tips though.&amp;nbsp; We will continue debugging it.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 12 Mar 2014 08:45:14 GMT</pubDate>
    <dc:creator>andyj25</dc:creator>
    <dc:date>2014-03-12T08:45:14Z</dc:date>
    <item>
      <title>PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258455#M25243</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, i want connect to i.MX6S PCIe LAN chip RTL8111E.&lt;/P&gt;&lt;P&gt;In RTL8111E PCIe pins is named as: HSI (input) and HSO (output) signal pair.&lt;/P&gt;&lt;P&gt;But i.MX6 datasheet not have information about PCIE_RX it is output or input pair.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Nov 2013 13:27:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258455#M25243</guid>
      <dc:creator>tarterkit_ru</dc:creator>
      <dc:date>2013-11-05T13:27:01Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258456#M25244</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi:&lt;BR /&gt;PCIE_TX is output, and PCIE_RX is input.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regard&lt;/P&gt;&lt;P&gt;Richard.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Dec 2013 02:05:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258456#M25244</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2013-12-06T02:05:23Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258457#M25245</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Hongxing Zhu,&lt;/P&gt;&lt;P&gt;I have a question.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the RTL8111E can be detected on the i.MX PCIe bus,&amp;nbsp; should I be able to see it on: &lt;EM&gt; /sys/bus/pci_express/devices&lt;/EM&gt;&amp;nbsp; ?&lt;/P&gt;&lt;P&gt;Currently I see nothing there.&amp;nbsp; Does that mean there's something wrong with my hardware?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 06:47:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258457#M25245</guid>
      <dc:creator>andyj25</dc:creator>
      <dc:date>2014-03-10T06:47:28Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258458#M25246</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;At least, you can see something by &lt;SPAN class="SpellE"&gt;lspci&lt;/SPAN&gt; command in Linux consol, if your &lt;SPAN class="SpellE"&gt;ep&lt;/SPAN&gt; device had been detected by &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;rc&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Richard.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 07:25:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258458#M25246</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-10T07:25:39Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258459#M25247</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Richard,&lt;/P&gt;&lt;P&gt;&lt;EM&gt;lspci&lt;/EM&gt; returns nothing.&lt;/P&gt;&lt;P&gt;Here is my schematic segment for the RTL8111E.&amp;nbsp; Can you spot anything wrong with it?&amp;nbsp; Thanks!!!&lt;/P&gt;&lt;P&gt;&lt;A href="http://i.imgur.com/D4dFP3g.jpg" title="http://i.imgur.com/D4dFP3g.jpg"&gt;http://i.imgur.com/D4dFP3g.jpg&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Mar 2014 07:30:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258459#M25247</guid>
      <dc:creator>andyj25</dc:creator>
      <dc:date>2014-03-10T07:30:41Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258460#M25248</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Hi:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Welcome.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;HW is out of my knowledge scope, you can make a reference to the &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; schematic of imx6 &lt;SPAN class="SpellE"&gt;sabresd&lt;/SPAN&gt; board of &lt;SPAN class="SpellE"&gt;fsl&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;I found there are some differences on the pull-down of the &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;clk&lt;/SPAN&gt; signals between your schematic and &lt;SPAN class="SpellE"&gt;fsl's&lt;/SPAN&gt; reference &lt;SPAN style="mso-spacerun:yes"&gt;&amp;nbsp;&lt;/SPAN&gt;schematic.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Hope it is helpful.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;BTW, I'm curious about your "detected” at your side, did the &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; link have been setup between &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;rc&lt;/SPAN&gt; and &lt;SPAN class="SpellE"&gt;ep&lt;/SPAN&gt;,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;and the &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;rc&lt;/SPAN&gt; allocate the &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; memory space and so on to &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; &lt;SPAN class="SpellE"&gt;ep&lt;/SPAN&gt;?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Richard&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 02:35:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258460#M25248</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-11T02:35:34Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258461#M25249</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Richard,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm loking at &lt;EM&gt;SPF-27516_C3.pdf.&lt;/EM&gt; There's no RTL8111E on that, but there is PCIe.&lt;/P&gt;&lt;P&gt;Are you referring to the 49.9Ω resistors pulling down CLK1_N and CLK1_P on the sabresd reference schematic?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Andrew&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 03:11:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258461#M25249</guid>
      <dc:creator>andyj25</dc:creator>
      <dc:date>2014-03-11T03:11:52Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258462#M25250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;Yes, it is.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 04:52:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258462#M25250</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-11T04:52:55Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258463#M25251</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Richard,&lt;/P&gt;&lt;P&gt;I will patch those resistors and report back here if it works.&lt;/P&gt;&lt;P&gt;In that schematic segment I posted there is also &lt;EM&gt;LAN_CLKREQ.&amp;nbsp;&amp;nbsp; &lt;/EM&gt;I have muxed it as a GPIO, but it is not implemented anywhere in my &lt;EM&gt;board-mx6q_sabresd.c&lt;/EM&gt;.&lt;/P&gt;&lt;P&gt;Is this pin critical for the operation of the PCIe bus?&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;&lt;SPAN&gt;Here's a segment from the datasheet: &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="http://i.imgur.com/lAfSahM.png"&gt;http://i.imgur.com/lAfSahM.png&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 07:06:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258463#M25251</guid>
      <dc:creator>andyj25</dc:creator>
      <dc:date>2014-03-11T07:06:45Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258464#M25252</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN style="font-size:14.0pt;mso-bidi-font-size:11.0pt"&gt;I think it is not critical for &lt;SPAN class="SpellE"&gt;pcie&lt;/SPAN&gt; if it is not used at all.&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Mar 2014 07:40:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258464#M25252</guid>
      <dc:creator>richard_zhu</dc:creator>
      <dc:date>2014-03-11T07:40:44Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe pins direction</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258465#M25253</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The added resistors didn't help.&amp;nbsp; Thanks for your tips though.&amp;nbsp; We will continue debugging it.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Mar 2014 08:45:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-pins-direction/m-p/258465#M25253</guid>
      <dc:creator>andyj25</dc:creator>
      <dc:date>2014-03-12T08:45:14Z</dc:date>
    </item>
  </channel>
</rss>

