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    <title>i.MX Processors中的主题 Why is access to V4L2 buffers slower than other memory?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146639#M248</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The reason for this is that the memory that the HW blocks like IPU and VPU must be non-cached. &amp;nbsp;As a result, the CPU operations are very slow versus similar operations using cached memory areas. &amp;nbsp;One way that you could get around this would be to allocate the memory as cached and then be sure to use cache maintenance routines to ensure coherency. &amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 19 Mar 2012 11:13:24 GMT</pubDate>
    <dc:creator>Philip_FSL</dc:creator>
    <dc:date>2012-03-19T11:13:24Z</dc:date>
    <item>
      <title>Why is access to V4L2 buffers slower than other memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146639#M248</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The reason for this is that the memory that the HW blocks like IPU and VPU must be non-cached. &amp;nbsp;As a result, the CPU operations are very slow versus similar operations using cached memory areas. &amp;nbsp;One way that you could get around this would be to allocate the memory as cached and then be sure to use cache maintenance routines to ensure coherency. &amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Mar 2012 11:13:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146639#M248</guid>
      <dc:creator>Philip_FSL</dc:creator>
      <dc:date>2012-03-19T11:13:24Z</dc:date>
    </item>
    <item>
      <title>Re: Why is access to V4L2 buffers slower than other memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146640#M249</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Philips,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Working on iMX6DL (Linux 3.14.28), I am try to pass user-space buffers to V4L2 for capture from a MIPI sensor (V4L2_BUFFER_USERPTR).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, I am not able to get any video using this method (with MMAP buffers it works fine).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I started a another thread about this - &lt;A href="https://community.nxp.com/thread/336875"&gt;V4L2_MEMORY_USERPTR Support&lt;/A&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you have any suggestions?&lt;/P&gt;&lt;P&gt;Any other method except USERPTR ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Erez&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Jul 2015 13:07:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146640#M249</guid>
      <dc:creator>erezsteinberg</dc:creator>
      <dc:date>2015-07-20T13:07:23Z</dc:date>
    </item>
    <item>
      <title>Re: Why is access to V4L2 buffers slower than other memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146641#M250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Here is an example of kernel driver that helps user space applications allocate cached buffers ready to use with V4L2 API (V4L2_MEMORY_USERPTR):&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/ikwzm/udmabuf" title="https://github.com/ikwzm/udmabuf"&gt;GitHub - ikwzm/udmabuf: User space mappable dma buffer device driver for Linux.&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;OBJECT data-extension-version="0.5.0.161" data-install-updates-user-configuration="true" data-supports-flavor-configuration="true" style="display: none;"&gt;&lt;/OBJECT&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Feb 2017 17:20:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Why-is-access-to-V4L2-buffers-slower-than-other-memory/m-p/146641#M250</guid>
      <dc:creator>joëlesponde</dc:creator>
      <dc:date>2017-02-03T17:20:47Z</dc:date>
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