<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: DRAM mux mapping to LPDDR2 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-mux-mapping-to-LPDDR2/m-p/256938#M24787</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sorry that the DDR3 and LPDDR2 pin mapping are different, and it can't be swap by SW setting. So fix it by HW modify is the only way.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 16 Aug 2013 09:54:02 GMT</pubDate>
    <dc:creator>aven_tsao</dc:creator>
    <dc:date>2013-08-16T09:54:02Z</dc:date>
    <item>
      <title>DRAM mux mapping to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-mux-mapping-to-LPDDR2/m-p/256937#M24786</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am having trouble getting the LPDDR2 SDRAM on my iMX6Q board to function. I used the pins shown in the the IMX6Q datasheet and the I/O Mux tool to define the pins. I just saw a table on page 3795 of the reference manual that talks about DRAM muxing for LPDDR2 pins being different than what is called out in the datasheet and I/O mux tool...........is this for real? Is there any way to get my board to work (other than hardware fixes) ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Kevin&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Aug 2013 12:23:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-mux-mapping-to-LPDDR2/m-p/256937#M24786</guid>
      <dc:creator>kbell_hardware</dc:creator>
      <dc:date>2013-08-15T12:23:42Z</dc:date>
    </item>
    <item>
      <title>Re: DRAM mux mapping to LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DRAM-mux-mapping-to-LPDDR2/m-p/256938#M24787</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sorry that the DDR3 and LPDDR2 pin mapping are different, and it can't be swap by SW setting. So fix it by HW modify is the only way.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Aug 2013 09:54:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DRAM-mux-mapping-to-LPDDR2/m-p/256938#M24787</guid>
      <dc:creator>aven_tsao</dc:creator>
      <dc:date>2013-08-16T09:54:02Z</dc:date>
    </item>
  </channel>
</rss>

