i.MX 8M Plus: RGMII to MII Migration – ENET_RXC / RX_ER Pin Assignment

Rameshkumar-PHYTEC — Fri, 25 Sep 2026 05:38:41 GMT

Hello NXP Community,

I am working on a custom Ethernet design using the NXP i.MX 8M Plus SoC with a PHYTEC phyCORE-i.MX8M Plus SOM.

We currently have an Ethernet design based on RGMII, and we are evaluating a migration from RGMII to MII for our custom board.

During the pinmux review, I found the following functions for the i.MX 8M Plus ENET_RXC pad:

ALT0: CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK
ALT1: ENET_QOS_RX_ER
ALT5: GPIO1_IO25

In our PHYTEC SOM allocation, this signal is associated with SOM pin A25.

My concern is related to the RGMII to MII migration. The required Ethernet signals are different between RGMII and MII.

I would like to clarify the following points:

1. Does the i.MX 8M Plus ENET_QOS MAC support a true MII interface in addition to RGMII and RMII?

2. If true MII is supported, what is the correct i.MX 8M Plus pin mapping for MII_RX_CLK, MII_RX_DV, MII_RX_ER, MII_RXD0 to MII_RXD3, MII_TX_CLK, MII_TX_EN, and MII_TXD0 to MII_TXD3?

3. For the ENET_RXC pad, is ALT0, CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK, intended only for RGMII, or can this function be used as the MII receive clock?

4. During an RGMII to MII migration, is ENET_QOS_RX_ER on the ENET_RXC pad required for the MII interface?

5. If MII_RX_ER is required, can it be assigned to another available i.MX 8M Plus pad through IOMUX, or is this signal internally associated with the ENET_RXC pad?

6. Since we are using a PHYTEC phyCORE-i.MX8M Plus SOM, are there any SOM routing limitations that need to be considered for implementing the MII interface?

7. If MII is supported, could someone provide an example or reference for the correct i.MX 8M Plus MII MAC-to-PHY pin configuration and device-tree configuration?

The reason for this clarification is that we are currently preparing the pinmux and schematic for a Bosch custom carrier board. We want to confirm the correct MII signal mapping before changing the SOM and carrier-board pin allocation.

The relevant pinmux information from our BSP is:

ENET_RXC
ALT0: CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK
ALT1: ENET_QOS_RX_ER
ALT5: GPIO1_IO25

Could someone please confirm whether a true RGMII-to-MII migration is supported on the i.MX 8M Plus ENET_QOS MAC and, if so, how ENET_RXC and RX_ER should be handled?

Thank you.

Re: i.MX 8M Plus: RGMII to MII Migration – ENET_RXC / RX_ER Pin Assignment

JosephAtNXP — Fri, 25 Sep 2026 16:45:50 GMT

Hi,

Thank you for your interest in NXP Semiconductor products,

This issue is related to this topic.

I will add in this thread the ENET_QOS details since they were not asked previously.

Neither ENET nor ENET_QOS / EQOS support MII, please refer to the following information from RM of EQOS:

RMII (10/100Mbps), RGMII (10/100/1000Mbps)

From DS:

1.8 V/3.3 V RMII operation, 1.8 V RGMII operation

Post mentions ENET signals interfacing EQOS signals. ENET signals correspond to ENET module, while ENET_QOS correspond to EQOS module, make sure to review that an available signal in PHYTEC SOM can be mapped to your desired function, you can base in pinfunc.h or config tools.

Download Config Tools for i.MX here.

Regards

topic Re: i.MX 8M Plus: RGMII to MII Migration – ENET_RXC / RX_ER Pin Assignment in i.MX Processors

i.MX 8M Plus: RGMII to MII Migration – ENET_RXC / RX_ER Pin Assignment

Re: i.MX 8M Plus: RGMII to MII Migration – ENET_RXC / RX_ER Pin Assignment