i.MX ProcessorsのトピックRe: Inline ECC validation method

Inline ECC validation method

pinkpr_6408 — Mon, 21 Sep 2026 11:35:46 GMT

Hello,

I am working on Inline ECC implementation for iMX8M Plus on external DDR memory.
ECC appears to be working (U-Boot modifications done, EDAC driver showing up in Linux, /sys/devices/system/edac/mc/mc0/ virtual files are present).

I'm looking for ways to test and validate the protection.

My understanding is that error injection is not possible into the data itself, and that ECC parity bits must be corrupted instead.

AN 13566 section 3.2.9 states : "Further information on this feature is available on request."

How can I request this information ? Is there a specific NXP contact/channel for this ?

Thank you in advance,

Re: Inline ECC validation method

natasha052gandhi — Tue, 22 Sep 2026 08:04:00 GMT

Hello,

I am implementing Inline ECC on an i.MX 8M Plus with external DDR. ECC appears to be working correctly: U-Boot has been configured, the Linux EDAC driver is active, and /sys/devices/system/edac/mc/mc0/ is present.

I would now like to validate the ECC protection by deliberately generating correctable and uncorrectable errors.

AN13566, section 3.2.9, states that Inline ECC errors can be injected by unlocking the ECC region using ECC_REGION_PARITY_LOCK and overriding the ECC parity bits. It also mentions that further information on this feature is available on request.

Re: Inline ECC validation method

AldoG — Tue, 22 Sep 2026 21:22:20 GMT

Hello,

Sure we can provide it, but for this I would require you to create a support ticket
https://support.nxp.com/s/?language=en_US

You may mention me in the body of the request so I can track the ticket and provide the material.

Best regards/Saludos,
Aldo.