topic Re: IMX8MP SDIO DDR50 clock issue in i.MX Processors

IMX8MP SDIO DDR50 clock issue

vishal088 — Mon, 31 Aug 2026 20:22:01 GMT

Hello

We recently applied the following NXP fix from kernel v7.2-rc4.

58c08eea91572df62d71731f1d1180a0dc8e3a6f
mmc: sdhci-esdhc-imx: fix esdhc_change_pinstate() to allow default state restore

Before this fix, esdhc_change_pinstate() required all pin control state named default, state_100mhz and state_200mhz to be present in device tree before applying any timing-specific pin control state. Therefore, if any pin control was not defined in the USDHC device-tree node, the driver did not apply state_100mhz, even when the SDIO device switched to DDR50 timing.
With the fix, the driver validates and applies only the pin control state required for the selected timing mode. Therefore, state_100mhz is now correctly applied for SDR50 and DDR50 modes.

After applying this fix, we observed an issue with the SD2 clock-pad configuration in state_100mhz.

SDIO device (in DDR50 mode) does not work with:

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194

However, SDIO device (in DDR50 mode) works with:

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x184
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196

The 0x184 setting differs from 0x194 only in slew rate. The other working settings use different drive-strength values.

We understand this behavior may be related to signal integrity. However, the result is not straightforward: DDR50 fails with 0x194, but works both with a slower slew rate (0x184) and with a stronger drive setting (0x196).

In addition, SDR50 works correctly with 0x194. The issue is observed only in DDR50 mode.

Could you please advise whether there are other i.MX8MP USDHC/SDIO configuration requirements or known limitations that we should consider? We would also appreciate any recommended debugging steps.

Regards
Vishal

Re: IMX8MP SDIO DDR50 clock issue

Zhiming_Liu — Tue, 01 Sep 2026 01:50:37 GMT

Hi @vishal088

Can you also share the SD2_DATA<X> setting?

Best Regards,
Zhiming

Re: IMX8MP SDIO DDR50 clock issue

vishal088 — Tue, 01 Sep 2026 08:13:11 GMT

Hi @Zhiming_Liu

for state_100mhz SD2_DATA<X> is 0x194.

Regards
Vishal

Re: IMX8MP SDIO DDR50 clock issue

Zhiming_Liu — Wed, 02 Sep 2026 03:08:03 GMT

Hi @vishal088

If you configure DATA and CMD to 0x1D4, then use set CLK to 0x194. Will the DDR50 fail again?

Can you please share the full usdhc dts node you are using? In addition, the SW team would like to know how you fixed usdhc to DDR50 mode.

Best Regards,
Zhiming

Re: IMX8MP SDIO DDR50 clock issue

vishal088 — Wed, 02 Sep 2026 09:49:42 GMT

Hi @Zhiming_Liu

Sry i typed wrong earlier. SD2_DATAx and SD2_CMD is 0x1d4 not 0x194 in my device tree for state_100mhz.

&usdhc2 {

pinctrl-names = "default", "state_100mhz";

pinctrl-0 = <&pinctrl_usdhc2>;

pinctrl-1 = <&pinctrl_usdhc2_100mhz>;

bus-width = <4>;

non-removable;

cap-power-off-card;

vmmc-supply = <&reg_wifi_ena>;

status = "okay";

};

pinctrl_usdhc2: usdhc2_grp {

fsl,pins = <

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190

MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1D0

MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1D0

MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1D0

MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1D0

MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1D0

};

pinctrl_usdhc2_100mhz: usdhc2_100mhz-grp {

fsl,pins = <

MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194

MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4

MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4

MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4

MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4

MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4

};

As we are not defining the state_200mhz pinctrl, in this function

esdhc_readl_le, driver(sdhci-esdhc-imx.c) remove the support for SDR104 and HS400 for host and keep the support for DDR50 and SDR50.

---- code

if (IS_ERR_OR_NULL(imx_data->pins_100mhz))

val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

if (IS_ERR_OR_NULL(imx_data->pins_200mhz))

val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);

and during the sdio attach phase it set the timing to DDR50 after negotiation with card about its capabilities.

same is verfied with "cat /sys/kernel/debug/mmc1/ios"
clock: 50000000 Hz
actual clock: 50000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 7 (sd uhs DDR50)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)

Note: we are using kernel 6.12.49 and we noticed the issue in "esdhc_change_pinstate" and after checking we found a fix from nxp on kernel 7.2-rc4. And after applying, it start using state_100mhz pinctrl state correctly but it break sdio device communication completely.
Later after playing with clock config as mentioned in earlier msg we narrowed that clk as 0x194 is the breaking config.

Regards
Vishal

Re: IMX8MP SDIO DDR50 clock issue

Zhiming_Liu — Thu, 03 Sep 2026 02:45:48 GMT

Hi @vishal088

I did tests on i.MX8MP EVK board with same setting in dts and kernel. For now, to speed up testing, I'm using the L6.18.20 kernel, but I don't think this issue has much to do with the kernel version.

Before using patch.

imx8mpevk login: root root@imx8mpevk:~# cat /sys/kernel/debug/mmc1/ios clock: 50000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 7 (sd uhs DDR50) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@imx8mpevk:~# dmesg | grep -i sd [ 2.445460] sdhci: Secure Digital Host Controller Interface driver [ 2.451674] sdhci: Copyright(c) Pierre Ossman [ 2.463953] sdhci-pltfm: SDHCI platform and OF driver helper [ 2.507075] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA [ 3.635632] sdhci-esdhc-imx 30b40000.mmc: allocated mmc-pwrseq [ 3.636284] sdhci-esdhc-imx 30b50000.mmc: Got CD GPIO [ 3.669847] mmc0: SDHCI controller on 30b40000.mmc [30b40000.mmc] using ADMA [ 3.682520] mmc1: SDHCI controller on 30b50000.mmc [30b50000.mmc] using ADMA [ 3.818728] mmc1: new UHS-I speed DDR50 SDHC card at address 59b4 [ 9.902634] imx-sdma 30e00000.dma-controller: firmware found. [ 9.902634] imx-sdma 30e10000.dma-controller: firmware found. [ 9.920146] imx-sdma 30bd0000.dma-controller: firmware found. [ 9.928124] imx-sdma 30bd0000.dma-controller: loaded firmware 4.6 root@imx8mpevk:~# lsblk NAME MAJ:MIN RM SIZE RO TYPE MOUNTPOINTS mtdblock0 31:0 0 32M 0 disk mmcblk2 179:0 0 29.2G 0 disk |-mmcblk2p1 179:1 0 256M 0 part /run/media/boot-mmcblk2p1 `-mmcblk2p2 179:2 0 10.5G 0 part / mmcblk2boot0 179:32 0 4M 1 disk mmcblk2boot1 179:64 0 4M 1 disk mmcblk1 179:96 0 29.8G 0 disk |-mmcblk1p1 179:97 0 256M 0 part /run/media/boot-mmcblk1p1 `-mmcblk1p2 179:98 0 12G 0 part /run/media/root-mmcblk1p2 root@imx8mpevk:~# cp /run/media/boot-mmcblk1p1/Image ./ root@imx8mpevk:~# ls -la Image -rwxr-x--- 1 root root 35678720 Mar 13 15:48 Image

After using patch, test read and write on SD card.

root@imx8mpevk:~# cp /run/media/boot-mmcblk1p1/tee.bin ./ root@imx8mpevk:~# cp tee.bin tee_test.bin root@imx8mpevk:~# cp tee_test.bin /run/media/boot-mmcblk1p1/ root@imx8mpevk:~# ls /run/media/boot-mmcblk1p1/ Image imx95-19x19-evk-dsi-serdes-jdi-wuxga-panel.dtb imx95-19x19-evk-os08a20-dual.dtb imx95-19x19-evk-ti-serdes-combo.dtb 'System Volume Information' imx95-19x19-evk-dsi-serdes-jdi-wuxga-panel.dtbo imx95-19x19-evk-os08a20-isp-it6263-lvds0.dtb imx95-19x19-evk-ti-serdes-combo.dtbo imx95-15x15-ab2.dtb imx95-19x19-evk-dsi-serdes.dtb imx95-19x19-evk-os08a20-isp-lvds-two-disp.dtb imx95-19x19-evk-ti-serdes.dtb imx95-15x15-evk-adv7535-ap1302.dtb imx95-19x19-evk-dsi-serdes.dtbo imx95-19x19-evk-os08a20.dtb imx95-19x19-evk-ti-serdes.dtbo imx95-15x15-evk.dtb imx95-19x19-evk-dual-os08a20-isp-it6263-lvds0.dtb imx95-19x19-evk-os08a20.dtbo imx95-19x19-evk-tja1104-rgmii.dtb imx95-15x15-frdm-8mic-reve.dtb imx95-19x19-evk-it6263-lvds-dual.dtb imx95-19x19-evk-ox03c10-all.dtb imx95-19x19-evk-tja1104-rmii.dtb imx95-15x15-frdm-ap1302.dtb imx95-19x19-evk-it6263-lvds-dual.dtbo imx95-19x19-evk-ox03c10-combo.dtb imx95-19x19-evk.dtb imx95-15x15-frdm-aud-hat.dtb imx95-19x19-evk-it6263-lvds-two-disp.dtb imx95-19x19-evk-ox03c10-combo.dtbo imx95-19x19-frdm-pro-aqr113c.dtb imx95-15x15-frdm-boe-wxga-lvds-panel.dtb imx95-19x19-evk-it6263-lvds0.dtb imx95-19x19-evk-ox03c10-isp-it6263-lvds0.dtb imx95-19x19-frdm-pro-aud-hat.dtb imx95-15x15-frdm-dual-os08a20-isp.dtb imx95-19x19-evk-it6263-lvds0.dtbo imx95-19x19-evk-ox03c10.dtb imx95-19x19-frdm-pro-dual-os08a20-isp.dtb imx95-15x15-frdm-neutron.dtb imx95-19x19-evk-it6263-lvds1.dtb imx95-19x19-evk-ox03c10.dtbo imx95-19x19-frdm-pro-inmate.dtb imx95-15x15-frdm-os08a20-combo-isp.dtb imx95-19x19-evk-it6263-lvds1.dtbo imx95-19x19-evk-ox05b1s-combo.dtb imx95-19x19-frdm-pro-neutron.dtb imx95-15x15-frdm-os08a20-isp.dtb imx95-19x19-evk-jdi-wuxga-lvds-panel.dtb imx95-19x19-evk-ox05b1s-combo.dtbo imx95-19x19-frdm-pro-os08a20-combo-isp.dtb imx95-15x15-frdm-root.dtb imx95-19x19-evk-jdi-wuxga-lvds-panel.dtbo imx95-19x19-evk-ox05b1s-isp-it6263-lvds0.dtb imx95-19x19-frdm-pro-os08a20-isp.dtb imx95-15x15-frdm-rpmsg.dtb imx95-19x19-evk-jtag.dtb imx95-19x19-evk-ox05b1s-isp-lvds-two-disp.dtb imx95-19x19-frdm-pro-root.dtb imx95-15x15-frdm-waveshare-7inch-c-panel.dtb imx95-19x19-evk-jtag.dtbo imx95-19x19-evk-ox05b1s.dtb imx95-19x19-frdm-pro-waveshare-7inch-c-panel.dtb imx95-15x15-frdm.dtb imx95-19x19-evk-lpspi-slave.dtb imx95-19x19-evk-ox05b1s.dtbo imx95-19x19-frdm-pro.dtb imx95-19x19-evk-adv7535-ap1302.dtb imx95-19x19-evk-lt9611uxc-ap1302.dtb imx95-19x19-evk-pcie1-ep.dtb imx95-jailhouse-inmate.dtb imx95-19x19-evk-adv7535.dtb imx95-19x19-evk-lt9611uxc.dtb imx95-19x19-evk-pcie1-ep.dtbo mcore-demos imx95-19x19-evk-adv7535.dtbo imx95-19x19-evk-lt9611uxc.dtbo imx95-19x19-evk-rm692c9.dtb tee.bin imx95-19x19-evk-ap1302.dtb imx95-19x19-evk-netc-rpmsg.dtb imx95-19x19-evk-rm692c9.dtbo tee_test.bin imx95-19x19-evk-ap1302.dtbo imx95-19x19-evk-neutron.dtb imx95-19x19-evk-root.dtb xen imx95-19x19-evk-cs42888.dtb imx95-19x19-evk-os08a20-combo.dtb imx95-19x19-evk-rpmsg.dtb imx95-19x19-evk-cs42888.dtbo imx95-19x19-evk-os08a20-combo.dtbo imx95-19x19-evk-sof.dtb

DTS modification, pinctrl_usdhc2_100mhz is default value from linux-imx. From the tests, we can see that these modifications didn't affect the SD card read/write under DDR50.

&usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; // pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; vmmc-supply = <&reg_usdhc2_vmmc>; bus-width = <4>; status = "okay"; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

So I think the problem you're experiencing right now might be related to the custom board. As it happens, 0x194 causes signal quality issues.

Best Regards

Zhiming