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    <title>topic IMX93 - Boot Cortex-M33 with Barebox in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-Boot-Cortex-M33-with-Barebox/m-p/2407033#M246467</link>
    <description>&lt;P&gt;Dear support team,&lt;/P&gt;&lt;P&gt;We are designing our custom board with an IMX9332C.&lt;/P&gt;&lt;P&gt;We chose not to use U-Boot as our bootloader, but Barebox instead, so sadly we cannot benefit from the work already done in uboot-imx. Our boot chain is as follows: TF-A → Barebox → Linux.&lt;BR /&gt;Versions: imx-atf lf-6.18.20-2.0.0, Barebox 2025.09.0 (custom board port), Linux 6.18.13.&lt;/P&gt;&lt;P&gt;We want to use the Cortex-M33 auxiliary core for our real-time-constrained features. The idea is to compile bare-metal code with the SDK, then load the resulting binary via the remoteproc framework from Linux.&lt;/P&gt;&lt;P&gt;I wrote and compiled a very simple C program that blinks an IO. When I load it with remoteproc, the framework reports that it has been loaded, but it does absolutely nothing. Whenever I stop it, it crashes.&lt;/P&gt;&lt;P&gt;My first guess was that the core wasn't correctly configured, so I dug into how u-boot prepares the M33 on NXP's FRDM reference board. I found that the M33 core has to be "prepared": its RAM must be zeroized, the watchdog configured, the TCM set up, etc. I ported some of these operations into my low-level initialization code in Barebox, but now when I load the code with remoteproc, it resets instantly.&lt;/P&gt;&lt;P&gt;At this point, I looked at the SRSR register to find the root cause of the reset, and the M33_REQ bit is set.&lt;/P&gt;&lt;P&gt;Looking at the documentation, this means a reset was requested by the Cortex-M33 itself.&lt;/P&gt;&lt;P&gt;I currently have no idea why this reset request is emitted; it isn't triggered anywhere in my own code.&lt;/P&gt;&lt;P&gt;Here are my questions:&lt;/P&gt;&lt;P&gt;Is there any documentation on the full requirements for "preparing" the M33?&lt;BR /&gt;What are the possible sources of a CM33_REQUEST reset ? Where could this come from?&lt;BR /&gt;Thank you.&lt;/P&gt;</description>
    <pubDate>Thu, 20 Aug 2026 12:50:36 GMT</pubDate>
    <dc:creator>jlablanche</dc:creator>
    <dc:date>2026-08-20T12:50:36Z</dc:date>
    <item>
      <title>IMX93 - Boot Cortex-M33 with Barebox</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-Boot-Cortex-M33-with-Barebox/m-p/2407033#M246467</link>
      <description>&lt;P&gt;Dear support team,&lt;/P&gt;&lt;P&gt;We are designing our custom board with an IMX9332C.&lt;/P&gt;&lt;P&gt;We chose not to use U-Boot as our bootloader, but Barebox instead, so sadly we cannot benefit from the work already done in uboot-imx. Our boot chain is as follows: TF-A → Barebox → Linux.&lt;BR /&gt;Versions: imx-atf lf-6.18.20-2.0.0, Barebox 2025.09.0 (custom board port), Linux 6.18.13.&lt;/P&gt;&lt;P&gt;We want to use the Cortex-M33 auxiliary core for our real-time-constrained features. The idea is to compile bare-metal code with the SDK, then load the resulting binary via the remoteproc framework from Linux.&lt;/P&gt;&lt;P&gt;I wrote and compiled a very simple C program that blinks an IO. When I load it with remoteproc, the framework reports that it has been loaded, but it does absolutely nothing. Whenever I stop it, it crashes.&lt;/P&gt;&lt;P&gt;My first guess was that the core wasn't correctly configured, so I dug into how u-boot prepares the M33 on NXP's FRDM reference board. I found that the M33 core has to be "prepared": its RAM must be zeroized, the watchdog configured, the TCM set up, etc. I ported some of these operations into my low-level initialization code in Barebox, but now when I load the code with remoteproc, it resets instantly.&lt;/P&gt;&lt;P&gt;At this point, I looked at the SRSR register to find the root cause of the reset, and the M33_REQ bit is set.&lt;/P&gt;&lt;P&gt;Looking at the documentation, this means a reset was requested by the Cortex-M33 itself.&lt;/P&gt;&lt;P&gt;I currently have no idea why this reset request is emitted; it isn't triggered anywhere in my own code.&lt;/P&gt;&lt;P&gt;Here are my questions:&lt;/P&gt;&lt;P&gt;Is there any documentation on the full requirements for "preparing" the M33?&lt;BR /&gt;What are the possible sources of a CM33_REQUEST reset ? Where could this come from?&lt;BR /&gt;Thank you.&lt;/P&gt;</description>
      <pubDate>Thu, 20 Aug 2026 12:50:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-Boot-Cortex-M33-with-Barebox/m-p/2407033#M246467</guid>
      <dc:creator>jlablanche</dc:creator>
      <dc:date>2026-08-20T12:50:36Z</dc:date>
    </item>
    <item>
      <title>Re: IMX93 - Boot Cortex-M33 with Barebox</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX93-Boot-Cortex-M33-with-Barebox/m-p/2407882#M246490</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/265791"&gt;@jlablanche&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;I hope you are doing very well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Unfortunately, we do not support the Barebox Bootloader in our platforms.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;But&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;you&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;can&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;take&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;as&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;started&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;point&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;chapter&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;4.7.4.1.4&lt;SPAN&gt;&amp;nbsp; i.MX&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;93&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;SPAN&gt;&amp;nbsp; i.MX&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;93W&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;from&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://www.nxp.com/docs/en/user-guide/UG10163.pdf" shape="rect" target="_blank"&gt;i.MX Linux User's Guide&lt;/A&gt;:&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 943px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/395188iFE8C99DB4737A01A/image-size/large?v=v2&amp;amp;px=999" role="button" title="image.png" alt="image.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;image.png&lt;/span&gt;&lt;/span&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;
&lt;DIV&gt;Here you can take a look to the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://nxp.lightning.force.com/lightning/r/Case/500Te00000f7shGIAQ/view" shape="rect" target="_blank"&gt;prepare_mcore&lt;/A&gt;.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Regarding to the CM33_REQUEST in SRSR.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;This can be because of the WDOG1 timeout.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;If your Barebox init code enabled WDOG1 but your bare-metal firmware does not service it in time, the watchdog expires and asserts SYSRESETREQ.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Best regards,&lt;/DIV&gt;
&lt;DIV&gt;Salas.&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Mon, 24 Aug 2026 20:56:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX93-Boot-Cortex-M33-with-Barebox/m-p/2407882#M246490</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2026-08-24T20:56:51Z</dc:date>
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