i.MX8MP: CSI0 with TP2860 encoder chip in continous clock mode

StefanB_emsys — Thu, 11 Jun 2026 10:11:28 GMT

Hi there,

we're trying to integrate a TP2860 video encoder in a IMX8MP based platform, but we're unable to capture any video. It seems the CSIS doesn't sync to incoming MIPI data stream.

Platform: Variscite DART-MX8M-PLUS on VAR CustomBoard
Kernel: linux-imx 6.6.52 (NXP BSP, imx8-mipi-csi2-sam driver), yocto build
Camera: TechPoint TP2860 MIPI encoder (AHD/TVI -> MIPI-CSI2 bridge), output MIPI clock: 297 MHz (measured)
Interface: CSI0 (mipi_csi_0 @ 0x32e40000), 2-lane, 500 Mbps/lane, FHD30 (1920x1080@30)
Pipeline: TP2860 -> MIPI D-PHY -> CSIS -> (MediaMix Gasket) -> ISI0 -> /dev/video2

The v4l2 pipeline looks ok (see attached pipeline_info.txt)

The relevant (flattened) devicetree info is attached in devicetree.txt.

DPHYSTATUS reports 0xC2 (all lanes in HS) but the
CSIS Frame Start counter is always zero (in fact, all mxc-mipi-csi2.0 counters are zero).

We have gone through NXP AN13857 and have a number of questions:

The TP2860 keeps its MIPI clock lane in HS between bursts (continuous clock mode). This is confirmed by CSIS DPHYSTATUS = 0xC2 both before and after drivers' s_stream enable:

=> CSIS register dump (CSIS base 0x32e40000):
CSIS_CMN_CTRL [0x04] = 0x00004105 (ENABLE=1, LANE_NR=1->2 lanes, HDR_MODE=0)
CSIS_DPHYCTRL [0x24] = 0x13000007 (hs_settle=0x13, D-PHY enabled)
CSIS_DPHYSTATUS [0x20] = 0x000000C2 (HSCLK=1, HSDAT1=1, STOPSTATE_CLK=0)
CSIS_INTSRC [0x14] = 0x00000000 (no interrupts fired)

=> CSIS_DPHYSTATUS[0x20] = 0x000000C2
bit 7: HSCLK = 1 (clock lane in HS)
bit 6: HSDAT1 = 1 (data lane 1 in HS)
bit 1: ULPS_CLK = 0 (not in ULPS)
bit 0: STOPSTATE_CLK = 0 (never in LP-11 stop state)

This matches the NXP AN13857 warning:
"i.MX 8MM, i.MX 8MN, and i.MX 8MP require the connected camera to work in the LP state
before enabling the Rx DPHY. But if the camera works in continuous clock mode, the clock
lane may always be in the HS mode. In this case, Rx DPHY may not detect the HS mode and
wrongly remains in the stop or ULPS state."

TP2860 register readback over I2C during streaming:
0x40 -> 0x08 (MIPI page selected by driver after s_stream)
0x02 -> 0x7d (MIPI_EN0=1, all bits set)
0x28 -> 0x00 (STOP_CLK=0, ULPM=0)
0x10 -> 0x20 (MIPI TX enabled, not in reset)
0x29 -> 0x00 (data lane stop/ULPS: none)

We tried to enable TP2860 internal BT.1120 test pattern (to rule out the analog encoder path):

0x40 -> 0x08 (MIPI page)
0x22 -> 0x80 (TP_ENA=1: bypass analog decoder, send digital pattern)

But that doesn’t improve the situation.

We’re setting up the TP2860 like this:

Write 0x02=0x3d, 0x03=0x35, 0x04=0x35 <-- MIPI_ENx=0 (lanes off)
Timing: 0x2B=0x09 (T_PREP reset default), 0x2C=0x0a
Decoder PLL reset: REG 0x06 |= 0x80, msleep(10)
MIPI PLL reset: REG 0x14 |= 0x80, msleep(10), deassert
msleep(50) (extended settle for PLL lock)
0x02=0x7d, 0x03=0x75, 0x04=0x75 <-- enable lanes (clean LP->HS)

Questions:

Is there a supported BSP mechanism to use the iMX8MP Rx D-PHY with a camera in continuous clock mode (STOPSTATE_CLK permanently 0)? Does the CSIS / D-PHY
have a mode that does not depend on observing LP-11 on the clock lane before asserting HS-RX enable?
Are there known errata or application notes beyond AN13857 for the iMX8MP regarding CSIS operation with continuous-clock MIPI-CSI2 sources?
The same hardware containing the TP2860 encoder chip works on a Boundary Devices i.MX8MQ setup

Any help is greatly appreciated.

Re: i.MX8MP: CSI0 with TP2860 encoder chip in continous clock mode

user101_einfo111112 — Tue, 14 Jul 2026 07:38:36 GMT

Hello,
I am facing the similar issue, can you please tell me if you found a solution for it.

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i.MX8MP: CSI0 with TP2860 encoder chip in continous clock mode

Re: i.MX8MP: CSI0 with TP2860 encoder chip in continous clock mode