<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Does i.MX95 support LPDDR5X memory?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392817#M245919</link>
    <description>&lt;DIV&gt;
&lt;UL&gt;
&lt;LI&gt;Yes, i.MX95 can work with many LPDDR5X devices, but only if those devices also support LPDDR5 backward-compatibility mode.&lt;/LI&gt;
&lt;LI&gt;i.MX95 does NOT support LPDDR5X-only devices.&amp;nbsp;&lt;/LI&gt;
&lt;LI&gt;Therefore, checking whether a memory is supported is not simply a matter of looking at MR8[1:0] or MR5 vendor ID alone.&lt;/LI&gt;
&lt;/UL&gt;
&lt;UL class=""&gt;
&lt;LI class=""&gt;&lt;STRONG class=""&gt;MR8[1:0] = 01 means the device is LPDDR5X-only&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;→ treat it as&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not supported&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for i.MX95, because NXP states LPDDR5X-only devices cannot be used.&lt;/LI&gt;
&lt;LI class=""&gt;&lt;STRONG class=""&gt;MR5 manufacturer/device ID is not in NXP’s validated list&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;→ it is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not validated by NXP&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, but that alone is not the same as “impossible.” You still need to confirm from the memory datasheet that the part supports LPDDR5 mode and matches the supported density/organization/timing constraints, then validate it in the board design.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/DIV&gt;</description>
    <pubDate>Thu, 09 Jul 2026 07:31:34 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2026-07-09T07:31:34Z</dc:date>
    <item>
      <title>Does i.MX95 support LPDDR5X memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392782#M245918</link>
      <description>&lt;P&gt;Does i.MX95 support LPDDR5X memory?&lt;/P&gt;&lt;P&gt;If MR8[1:0]=01 or MR5 ID is not in your support list&lt;/P&gt;&lt;P&gt;How do i.MX95 check supported or not? check MR register?&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jul 2026 06:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392782#M245918</guid>
      <dc:creator>jimmychang</dc:creator>
      <dc:date>2026-07-09T06:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: Does i.MX95 support LPDDR5X memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392817#M245919</link>
      <description>&lt;DIV&gt;
&lt;UL&gt;
&lt;LI&gt;Yes, i.MX95 can work with many LPDDR5X devices, but only if those devices also support LPDDR5 backward-compatibility mode.&lt;/LI&gt;
&lt;LI&gt;i.MX95 does NOT support LPDDR5X-only devices.&amp;nbsp;&lt;/LI&gt;
&lt;LI&gt;Therefore, checking whether a memory is supported is not simply a matter of looking at MR8[1:0] or MR5 vendor ID alone.&lt;/LI&gt;
&lt;/UL&gt;
&lt;UL class=""&gt;
&lt;LI class=""&gt;&lt;STRONG class=""&gt;MR8[1:0] = 01 means the device is LPDDR5X-only&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;→ treat it as&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not supported&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for i.MX95, because NXP states LPDDR5X-only devices cannot be used.&lt;/LI&gt;
&lt;LI class=""&gt;&lt;STRONG class=""&gt;MR5 manufacturer/device ID is not in NXP’s validated list&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;→ it is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG class=""&gt;not validated by NXP&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;, but that alone is not the same as “impossible.” You still need to confirm from the memory datasheet that the part supports LPDDR5 mode and matches the supported density/organization/timing constraints, then validate it in the board design.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/DIV&gt;</description>
      <pubDate>Thu, 09 Jul 2026 07:31:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392817#M245919</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2026-07-09T07:31:34Z</dc:date>
    </item>
    <item>
      <title>Re: Does i.MX95 support LPDDR5X memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392831#M245920</link>
      <description>&lt;P&gt;As you said "MR8[1:0] = 01 means the device is LPDDR5X-only&amp;nbsp;"&lt;/P&gt;&lt;P&gt;MR8[1:0]=00 support LPDDR5,&amp;nbsp;MR8[1:0]=01 support&amp;nbsp;LPDDR5x.&lt;/P&gt;&lt;P&gt;So what should&amp;nbsp;MR8[1:0]=?? support&amp;nbsp;LPDDR5 and&amp;nbsp;LPDDR5x ?&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jul 2026 07:49:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392831#M245920</guid>
      <dc:creator>jimmychang</dc:creator>
      <dc:date>2026-07-09T07:49:52Z</dc:date>
    </item>
    <item>
      <title>Re: Does i.MX95 support LPDDR5X memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392843#M245921</link>
      <description>&lt;P&gt;Per JEDEC LPDDR5/LPDDR5X definitions:&lt;/P&gt;
&lt;TABLE&gt;
&lt;TBODY&gt;
&lt;TR&gt;
&lt;TD&gt;
&lt;P&gt;&lt;STRONG&gt;MR8[1:0]&lt;/STRONG&gt;&lt;/P&gt;
&lt;/TD&gt;
&lt;TD&gt;
&lt;P&gt;&lt;STRONG&gt;Meaning&lt;/STRONG&gt;&lt;/P&gt;
&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;
&lt;P&gt;00b&lt;/P&gt;
&lt;/TD&gt;
&lt;TD&gt;
&lt;P&gt;LPDDR5 capable&lt;/P&gt;
&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;
&lt;P&gt;01b&lt;/P&gt;
&lt;/TD&gt;
&lt;TD&gt;
&lt;P&gt;LPDDR5X capable&lt;/P&gt;
&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;
&lt;P&gt;10b&lt;/P&gt;
&lt;/TD&gt;
&lt;TD&gt;
&lt;P&gt;Reserved&lt;/P&gt;
&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR&gt;
&lt;TD&gt;
&lt;P&gt;11b&lt;/P&gt;
&lt;/TD&gt;
&lt;TD&gt;
&lt;P&gt;Reserved&lt;/P&gt;
&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;
&lt;P&gt;The problem is that &lt;STRONG&gt;MR8 only reports the mode family implemented by the device&lt;/STRONG&gt;, but it does &lt;STRONG&gt;not tell you whether the device can also operate in the other mode&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;Example&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;Consider a Samsung part advertised as LPDDR5X.&lt;/P&gt;
&lt;P&gt;The device may:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Be an LPDDR5X device that is backward compatible with LPDDR5.&lt;/LI&gt;
&lt;LI&gt;Power up reporting MR8[1:0]=01.&lt;/LI&gt;
&lt;LI&gt;Still be fully usable on i.MX95 because it supports LPDDR5 operation.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;NXP's compatibility guide explicitly mentions that many memories marketed as "LPDDR5X" are actually backward-compatible with LPDDR5 and can therefore be used with i.MX95.&lt;/P&gt;
&lt;P&gt;Then&amp;nbsp;&lt;STRONG&gt;MR8[1:0] is an identification field, not a capability bitmap&lt;/STRONG&gt;&amp;nbsp;. So a dual-capable / backward-compatible LPDDR5X-marketed device normally has to be checked from the&amp;nbsp;&lt;STRONG&gt;DRAM datasheet&lt;/STRONG&gt;&amp;nbsp;, not inferred from a special MR8 “both” code.&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jul 2026 08:10:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392843#M245921</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2026-07-09T08:10:20Z</dc:date>
    </item>
    <item>
      <title>Re: Does i.MX95 support LPDDR5X memory?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392853#M245922</link>
      <description>&lt;P&gt;Thanks for your quickly apply.&lt;/P&gt;</description>
      <pubDate>Thu, 09 Jul 2026 08:25:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-i-MX95-support-LPDDR5X-memory/m-p/2392853#M245922</guid>
      <dc:creator>jimmychang</dc:creator>
      <dc:date>2026-07-09T08:25:11Z</dc:date>
    </item>
  </channel>
</rss>

