NXP iMX95: ARM SMMU problem with PCIe

pierluigi_p — Wed, 27 May 2026 21:22:02 GMT

Dear NXP support,

we are trying to integrate a PCIe-USB bridge eval kit (https://www.microchip.com/en-us/development-tool/ev96n38a) with NXP iMX95 using kernel 6.12.49.

The PCIe bridge successfully completes PCIe enumeration and all endpoints (xHCI controller, i2c controller, etc.) show up when running "lspci".

When plugging in a USB device (flash drive, keyboard, etc.) to a USB port on the PCI11400 eval kit, the following messages are listed

[ 1631.912942] arm-smmu-v3 490d0000.iommu: event 0x10 received:
[ 1631.918618] arm-smmu-v3 490d0000.iommu: 0x0000001000000010
[ 1631.924188] arm-smmu-v3 490d0000.iommu: 0x0000020200000000
[ 1631.929760] arm-smmu-v3 490d0000.iommu: 0x0000000000000000
[ 1631.935326] arm-smmu-v3 490d0000.iommu: 0x0000000000000000

but no USB device is actually enumerated.

Suspecting some kind of problem with ARM SMMU translation we added "iommu.passthrough=1" to the kernel command line: with this change, the USB devices are correctly enumerated.

However, "iommu.passthrough=1" allows accessing to protected memory regions (i.e. encryption keys) and cannot be considered a valid workaround from a security perspective.

Could you propose any alternative solution ?

Thanks

Best Regards

Pier

Re: NXP iMX95: ARM SMMU problem with PCIe

Zhiming_Liu — Thu, 28 May 2026 06:59:45 GMT

Hi @pierluigi_p

It looks like that the PCIe-USB bridge you are using is accessing SMMU IDs other than the SID and RID allowed by the i.MX95 PCI node.

Below are the SMMU settings for the i.mx95 PCIe. i think you should figure out the actual SID and RID mapping used by the PCI11400.

iommu-map = <0x000 &smmu 0x10 0x1>, <0x100 &smmu 0x11 0x7>; iommu-map-mask = <0x1ff>;

Best Regards,
Zhiming

Re: NXP iMX95: ARM SMMU problem with PCIe

pierluigi_p — Thu, 04 Jun 2026 10:20:58 GMT

Hi @Zhiming_Liu,

thanks for the suggestion.

Best Regards

Pier

topic Re: NXP iMX95: ARM SMMU problem with PCIe in i.MX Processors

NXP iMX95: ARM SMMU problem with PCIe

Re: NXP iMX95: ARM SMMU problem with PCIe

Re: NXP iMX95: ARM SMMU problem with PCIe