IMX8MP: I2C clock strange behavior

Chantale — Sat, 02 May 2026 16:24:17 GMT

I'm having a strange issue on IMX8MP with the I2C bus.

I2C used is I2C5 (muxed out from HDMI)
The bus uses a TXS0102 1.8 to 3.3 shifter
10k pullups on the 3.3 side (+ internal 10k pullups on both that are bypssed by one-shot)
Linux FSLC kernel
100 kHz clock (although the scope would lead me to believe it's 200 kHz?)

I've been having random bus glitches particularly with multple devices connected so I isolated the situation to a single slave connected with a short ~5 cm cable. The slave reacts correctly to enumeration, but after the 9th clock cycle the clock goes low and stays low for a while (I've seen values from less than 50 µs to 600+ µs). There's also a repeatable glitch on SDA during the low phase of the 8th clock cycle which may or may not be related to anything. Scope session probed at the 3.3v side:

After a while SDA is pulled low again (by who?), SCL is released high and eventually SDA is relesed too. Checked this with:

Two different slaves
Addressing a non-existing slave
No slaves bus (just an empty connector)

I'll study it further, but if anyone knows what's up with this out of their head, would be greatly appreciated.

Re: IMX8MP: I2C clock strange behavior

Chantale — Sun, 03 May 2026 16:37:49 GMT

FET-shifted I²C behaves similarly too (CSI bus):

Re: IMX8MP: I2C clock strange behavior

Manuel_Salas — Mon, 04 May 2026 19:08:30 GMT

Hello @Chantale

I hope you are doing very well.

Could you please share your device tree?

Also, if possible, the schematic related to the I2C5.

Best regards,

Salas.

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IMX8MP: I2C clock strange behavior

Re: IMX8MP: I2C clock strange behavior

Re: IMX8MP: I2C clock strange behavior